A simple semiempirical model I D (V GS , V DS ) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called "top-ofthe-barrier-transport" model, and we refer to it as the "virtual source" (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage V GS = V dd ); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically I off at V GS = 0 V) and at high V DS ; 5) total resistance at V DS = 0 V and V GS = V dd and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection.

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Prospects of velocity enhancement as the main driver of performance scaling in future CMOS are examined. Limits of velocity enhancement in uniaxially strained Si are first presented and then outlooks of novel channel materials such as Ge and III-V semiconductors are discussed. Finally, characteristics of performance scaling under power dissipation constraints are studied.

Metal-oxide-semiconductor field effect transistors (MOSFET) with a thin high-k dielectric were fabricated on bulk n-type germanium substrates. Surface oxides were thermally desorbed in situ by heating the substrates under ultrahigh vacuum conditions. First an ultrathin passivating layer was formed by evaporating germanium in the presence of atomic oxygen and nitrogen supplied from a remote radio frequency plasma source. Subsequently, the HfO2 dielectric was deposited by evaporating hafnium in the presence of atomic oxygen. An in situ TaN metal gate was similarly deposited. Long channel devices were fabricated using a standard process flow. These devices exhibited a low equivalent oxide thickness (EOT) of 0.7nm with gate leakage less than 15mA∕cm2 at VFB+1V. Device mobility was extracted from Is-Vg and split C-V characteristics. Results indicate a 2× mobility enhancement in Ge p-MOSFET devices compared to Si control devices. The demonstration of subnanometer EOT suggests that high-k gate dielectrics on germanium are scalable to low EOT and suitable for use in ultrascaled MOSFET devices.

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