A simple semiempirical model I D (V GS , V DS ) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called "top-ofthe-barrier-transport" model, and we refer to it as the "virtual source" (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage V GS = V dd ); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically I off at V GS = 0 V) and at high V DS ; 5) total resistance at V DS = 0 V and V GS = V dd and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection.
Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gatecontrolled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained-Si/strained-Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained-Si/strained-Ge/relaxed Si 0.5 Ge 0.5 heterojunctions is used to extract a valence band offset of 0.64 eV at the strained-Si/strained-Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low-operating-voltage (V dd < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.
Strained pseudomorphic Si/Si 1−x Ge x /Si gatecontrolled band-to-band tunneling (BTBT) devices have been analyzed with varying Ge composition up to 57% and p+ tunneljunction (source) doping concentration in the 10 19 −10 20 cm −3 range. Measurements show the impact of these parameters on the transfer and output characteristics. Measurements are compared to simulations using a nonlocal BTBT model to analyze the mechanisms of device operation and to understand the impact of these parameters on the device switching behavior. The measured characteristics are consistent with simulation analysis that shows a reduction in energy barrier for tunneling (E geff ) and a reduction in tunneling distance with increasing Ge composition and source doping concentration. Increases in the pseudomorphic layer Ge content and doping concentration of the tunnel junction produce large improvements in the measured switching-behavior characteristics (I on , slope, turn-on voltages, and sharpness of turn-on as a function of V ds ). Simulations are also performed to project the potential performance of more optimized structures that may be suitable for extremely low power applications (V dd < 0.4 V).
We report for the first time on graphene transistors that incorporate a remote plasma-assisted atomic-layer-deposited Al 2 O 3 gate dielectric that is directly deposited to chemical-vapordeposited monolayer graphene at 100 • C. Following dielectric formation, atomic force microscopy and Raman measurements show apparently uniform conformal coverage and retention of a nearly intact film with a slightly increased level of disorder and some signs of additional doping. Using this process, 3-μm gate length transistors with sub-10-nm gate insulator thickness are constructed, and electrical measurements demonstrate a drive current of 0.6 A/mm and a peak transconductance in excess of 90 mS/mm with V gs = 0 V and V ds = 1 V, which is greatly improved over coprocessed devices with SiO 2 interfacial layer with the same bias. With optimization, the plasma-assisted ALD of high-k dielectrics to graphene may potentially be useful for the design of future graphene-based technology.
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