MOSFET Performance Scaling—Part I: Historical Trends

Khakifirooz, A.; Antoniadis, D.A.

doi:10.1109/ted.2008.921017

Cited by 104 publications

(71 citation statements)

References 82 publications

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“…A simplified version of the alpha-power law was proposed in [18]. More recently, a simple analytical expression for the intrinsic MOSFET delay, using physics-based models for the effective current and the total gate switching charge, was proposed to better describe nanometric technologies [19], [20].…”

Section: Model For Delay and Output Slewmentioning

confidence: 99%

“…Recent studies [21]- [23] show that the simple C load V dd /I dsat metric follows the experimental inverter delay much better if the on-current in the denominator is replaced with an effective current I ef f representing the average switching current. In line with the intrinsic transistor delay defined in [19], we model cell delay as…”

Section: Model For Delay and Output Slewmentioning

confidence: 99%

“…and can be evaluated easily through performance modeling or through a circuit simulation that takes into account process variations [19], [24]. Since our focus is to model delay and output slew as functions of input variables, (1) and (2), we assume we know I ef f for each input vector.…”

Section: Model For Delay and Output Slewmentioning

confidence: 99%

See 2 more Smart Citations

Statistical Library Characterization using Belief Propagation across Multiple Technology Nodes

Liu

Saxena

Hess

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-In this paper, we propose a novel flow to enable computationally efficient statistical characterization of delay and slew in standard cell libraries. The distinguishing feature of the proposed method is the usage of a limited combination of output capacitance, input slew rate and supply voltage for the extraction of statistical timing metrics of an individual logic gate. The efficiency of the proposed flow stems from the introduction of a novel, ultra-compact, nonlinear, analytical timing model, having only four universal regression parameters. This novel model facilitates the use of maximum-a-posteriori belief propagation to learn the prior parameter distribution for the parameters of the target technology from past characterizations of library cells belonging to various other technologies, including older ones. The framework then utilises Bayesian inference to extract the new timing model parameters using an ultra-small set of additional timing measurements from the target technology. The proposed method is validated and benchmarked on several production-level cell libraries including a state-of-the-art 14-nm technology node and a variation-aware, compact transistor model. For the same accuracy as the conventional lookup-table approach, this new method achieves at least 15x reduction in simulation runs.

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Section: Model For Delay and Output Slewmentioning

confidence: 99%

Section: Model For Delay and Output Slewmentioning

confidence: 99%

See 1 more Smart Citation

Statistical Library Characterization using Belief Propagation across Multiple Technology Nodes

Liu

Saxena

Hess

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

View full text Add to dashboard Cite

show abstract

“…22. Based on the "charge-sheet approximation", the saturation I ds of the nanoscale transistor can be described by the product of the local charge density and the carrier velocity, as follows (Khakifirooz & Antoniadis, 2008). The virtual source charge density (Q xio ) is given by (Khakifirooz et al, 2009),…”

Section: Source Drain Channelmentioning

confidence: 99%

The Evolution of Theory on Drain Current Saturation Mechanism of MOSFETs from the Early Days to the Present Day

Yang¹,

Lai²,

Chan³

2010

Solid State Circuits Technologies

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“…While the MOSFET undergoes scaling down of the size in order to improve integrated circuit performance such as speed, power consumption, and packing density, a number of challenges need to be overcome. This improvement in device speed and the shrinking of dimensions has continued successfully for over 30 years, as predicted by Moore's Law more than 40 years ago [1]. While the performance and density of the device is expected to be higher with the shrinking of the gate length, some challenges on the ordinary, lateral MOS device arose [2].…”

Section: Introductionmentioning

confidence: 99%

Investigation of Short Channel Effect on Vertical Structures in Nanoscale Mosfet

2009

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Abstrak Keywords: vertical MOSFET, devais ukuran nano, short channel effect, fabrication INTRODUCTIONThe recent development of MOSFET has reached the progress that the channel length goes shorter into nanometer scale. While the MOSFET undergoes scaling down of the size in order to improve integrated circuit performance such as speed, power consumption, and packing density, a number of challenges need to be overcome. This improvement in device speed and the shrinking of dimensions has continued successfully for over 30 years, as predicted by Moore's Law more than 40 years ago [1]. While the performance and density of the device is expected to be higher with the shrinking of the gate length, some challenges on the ordinary, lateral MOS device arose [2]. This dimension reduction has the biggest impact on lithography, as the key equipment for transferring design features onto substrate. When the device resolution goes smaller, it gives the consequences for the use of lithography source wavelength. As a rule of thumb, the resolution of lithography is about half of the wavelength of its source [3]. Thus, with channel length goes into sub-100 nm in length, the lithography had to be into deep UV or even in the x-ray region, which eventually lead to more expensive and sophisticate equipment installment. With it, the cost of manufacturing and also its complexity tend to increase dramatically. Other challenges over the channel scaling are the short channel effects. The short channel effect includes threshold voltage reduction, increasing dissipation

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MOSFET Performance Scaling—Part I: Historical Trends

Cited by 104 publications

References 82 publications

Statistical Library Characterization using Belief Propagation across Multiple Technology Nodes

Statistical Library Characterization using Belief Propagation across Multiple Technology Nodes

The Evolution of Theory on Drain Current Saturation Mechanism of MOSFETs from the Early Days to the Present Day

Investigation of Short Channel Effect on Vertical Structures in Nanoscale Mosfet

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