Investigation of Short Channel Effect on Vertical Structures in Nanoscale Mosfet

Abstract

Abstrak Keywords: vertical MOSFET, devais ukuran nano, short channel effect, fabrication INTRODUCTIONThe recent development of MOSFET has reached the progress that the channel length goes shorter into nanometer scale. While the MOSFET undergoes scaling down of the size in order to improve integrated circuit performance such as speed, power consumption, and packing density, a number of challenges need to be overcome. This improvement in device speed and the shrinking of dimensions has continued successfully for over 30 years, as predicted by Moore's Law more than 40 years ago [1]. While the performance and density of the device is expected to be higher with the shrinking of the gate length, some challenges on the ordinary, lateral MOS device arose [2]. This dimension reduction has the biggest impact on lithography, as the key equipment for transferring design features onto substrate. When the device resolution goes smaller, it gives the consequences for the use of lithography source wavelength. As a rule of thumb, the resolution of lithography is about half of the wavelength of its source [3]. Thus, with channel length goes into sub-100 nm in length, the lithography had to be into deep UV or even in the x-ray region, which eventually lead to more expensive and sophisticate equipment installment. With it, the cost of manufacturing and also its complexity tend to increase dramatically. Other challenges over the channel scaling are the short channel effects. The short channel effect includes threshold voltage reduction, increasing dissipation