Statistical Library Characterization using Belief Propagation across Multiple Technology Nodes

Abstract

Abstract-In this paper, we propose a novel flow to enable computationally efficient statistical characterization of delay and slew in standard cell libraries. The distinguishing feature of the proposed method is the usage of a limited combination of output capacitance, input slew rate and supply voltage for the extraction of statistical timing metrics of an individual logic gate. The efficiency of the proposed flow stems from the introduction of a novel, ultra-compact, nonlinear, analytical timing model, having only four universal regression parameters. This novel model facilitates the use of maximum-a-posteriori belief propagation to learn the prior parameter distribution for the parameters of the target technology from past characterizations of library cells belonging to various other technologies, including older ones. The framework then utilises Bayesian inference to extract the new timing model parameters using an ultra-small set of additional timing measurements from the target technology. The proposed method is validated and benchmarked on several production-level cell libraries including a state-of-the-art 14-nm technology node and a variation-aware, compact transistor model. For the same accuracy as the conventional lookup-table approach, this new method achieves at least 15x reduction in simulation runs.

VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models

“…µ model and σ model are the mean and standard deviation of estimated delay distribution using proposed models while µ S PICE and σ S PICE are captured from SPICE Monte Carlo simulations as golden results. The results of [14] are worse than these shown in their paper since the temperature is a constant in their models, which is an important parameter demonstrated in Figure 7. As the slib is built under quadratic fittings and MARS, it is much slower in building the slib library comparing to other works.…”

“…Figure 2 shows the modeling process of the statistical standard cell library (slib). The mean of the cell delay is considered as a function of operating conditions while delay variations are quantified by considering the PV influences [7] [14]. The operating conditions (V dd ,T, S in , C L ) are also considered in [14] and in traditional industrial corner-based standard cell libraries [15].…”

“…The mean of the cell delay is considered as a function of operating conditions while delay variations are quantified by considering the PV influences [7] [14]. The operating conditions (V dd ,T, S in , C L ) are also considered in [14] and in traditional industrial corner-based standard cell libraries [15]. The input sets for regressions are PVs, sampled from Monte Carlo simulations which are only required once for all standard cells under a specific technology node.…”

AI/ML Algorithms and Applications in VLSI Design and Technology

“…Yu et.al [77] proposed a novel nonlinear analytical timing model for statistical characterization of the delay and slew of standard library cells in bulk silicon, SOI technologies, and non-FinFET and FinFET technologies, using a limited combination of output capacitance, input slew rate, and supply voltage. Their framework utilized Bayesian inference to extract the new timing model parameters using an ultrasmall set of additional timing measurements from the target technology, achieving a 15× runtime speedup in simulation runs without compromising on accuracy, which is better than the traditional lookup table approach.…”