Articles you may be interested inMechanical tensile strain induced gate and substrate currents change in n and p-channel metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 101, 053507 (2012); 10.1063/1.4740278 Characterization of fast charge trapping in bias temperature instability in metal-oxide-semiconductor field effect transistor with high dielectric constant Appl. Phys. Lett. 96, 142110 (2010); 10.1063/1.3384999 The positive bias temperature instability of n -channel metal-oxide-semiconductor field-effect transistors with Zr O 2 gate dielectric Appl. Phys. Lett. 92, 202901 (2008); 10.1063/1.2928235Improved gate oxide integrity of strained Si n -channel metal oxide silicon field effect transistors using thin virtual substrates Characterization of atomic-layer-deposited silicon nitride / SiO 2 stacked gate dielectrics for highly reliable pmetal-oxide-semiconductor field-effect transistors

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Integrated circuits have to be robust to manufacturing variations. This paper presents a new statistical methodology to determine the worst-case corners for a set of circuit performances. Our methodology first estimates response surfaces for circuit performances as quadratic functions of the process parameters with known statistical distributions. These response surface models are then used to extract the worst-case corners in the process parameter space as the points where the circuit performances are at their min/max values corresponding to a specified statistical level. Corners in the process parameter space close to each other are clustered to reduce their number, which reduces the number of simulations required for design verification. We introduce the novel concept of relaxation coefficient to ensure that the corners capture the min/max values of all the circuit performances at the desired statistical level. The corners are realistic since they track the multivariate statistical distribution of the process parameters. Expected worstcase circuit performances can thus be extracted with a small number of simulations suitable for subsequent design verifications. The methodology is demonstrated with examples showing extraction of corners from digital standard cells and also the corners for analog/RF blocks found in typical communication ICs.

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There exists a complex and multifactorial relationship between diabetes and cardiovascular disease. Hyperglycemia is an important factor imposing damage (glucose toxicity) on cardiac cell leading to diabetic cardiomyopathy. There are substantial clinical evidences on the adverse effects of conventional therapies in the prevention/treatment of diabetic cardiovascular complications. Currently, green-synthesized nanoparticles have emerged as a safe, efficient, and inexpensive alternative for therapeutic uses. The present study discloses the silver nanoparticle biosynthesizing capability and cardioprotective potential of Syzygium cumini seeds already reported to have antidiabetic properties. Newly generated silver nanoparticles S. cumini MSE silver nanoparticles (SmSNPs) were characterized by UV-visible spectroscopy, scanning electron microscopy (SEM), zeta sizer, X-ray diffraction (XRD), and Fourier transform infrared (FTIR) spectroscopy. Using methanolic extract of S. cumini seeds, an average size of 40-100-nm nanoparticles with 43.02 nm and -19.6 mV zeta potential were synthesized. The crystalline nature of SmSNPs was identified by using XRD. 2,2-Diphenyl-1-picrylhydrazyl (DPPH) and 2,2'-azino-bis(3-ethylbenzthiazoline-6-sulfonic acid (ABTS) assays revealed the antioxidative potential to be 66.87 (±0.7) % and 86.07 (±0.92) % compared to 60.29 (±0.02) % and 85.67 (±1.27) % for S. cumini MSE. In vitro study on glucose-stressed H9C2 cardiac cells showed restoration in cell size, nuclear morphology, and lipid peroxide formation upon treatment of SmSNPs. Our findings concluded that S. cumini MSE SmSNPs significantly suppress the glucose-induced cardiac stress in vitro by maintaining the cellular integrity and reducing the oxidative damages therefore establishing its therapeutic potential in diabetic cardiomyopathy.

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In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as VT and IDSS, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution networ

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