Heterojunction tunneling field-effect transistors (HTFETs) that use strained-silicon/strained-germanium type-II staggered band alignment for band-to-band tunneling (BBT) injection are simulated using a nonlocal quantum tunneling model. The tunneling model is first compared to measurements of gatecontrolled BBT in previously fabricated strained SiGe diodes and is shown to produce good agreement with the measurements. The simulation of the gated diode structure is then extended to study HTFETs with an effective energy barrier of 0.25 eV at the strained-Si/strained-Ge heterointerface. As the band alignment, particularly the valence band offset, is critical to modeling HTFET operation, analysis of measured characteristics of MOS capacitors fabricated in strained-Si/strained-Ge/relaxed Si 0.5 Ge 0.5 heterojunctions is used to extract a valence band offset of 0.64 eV at the strained-Si/strained-Ge heterointerface. Simulations are used to compare HTFETs to MOSFETs with similar technology parameters. The simulations show that HTFETs have potential for low-operating-voltage (V dd < 0.5 V) application and exhibit steep subthreshold swing over many decades while maintaining high ON-state currents.

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The effects of high-level uniaxial tensile strain on the performance of gate-all-around (GAA) Si n-MOSFETs are investigated for nanowire (NW) diameters down to 8 nm. Suspended strained-Si NWs with ∼2-GPa uniaxial tension were realized by nanopatterning-induced unilateral relaxation of ultrathin-body 30% strained-Si-directly-on-insulator substrates. Based on these NWs, GAA strained-Si n-MOSFETs were fabricated with a Si thickness of ∼8 nm and NW widths in the range of 50 nm down to 8 nm. The GAA strained-Si MOSFETs show excellent subthreshold swing and cutoff behavior, and approximately two times current drive and intrinsic transconductance enhancement compared to similar unstrained Si devices.

Hole mobility and velocity are extracted from scaled strained-Si 0.45 Ge 0.55 channel p-MOSFETs on insulator. Devices have been fabricated with sub-100-nm gate lengths, demonstrating hole mobility and velocity enhancements in strained-Si 0.45 Ge 0.55 channel devices relative to Si. The effective hole mobility is extracted utilizing the dR/dL method. A hole mobility enhancement is observed relative to Si hole universal mobility for shortchannel devices with gate lengths ranging from 65 to 150 nm. Hole velocities extracted using several different methods are compared. The hole velocity of strained-SiGe p-MOSFETs is enhanced over comparable Si control devices. The hole velocity enhancements extracted are on the order of 30%. Ballistic velocity simulations suggest that the addition of 110 uniaxial compressive strain to Si 0.45 Ge 0.55 can result in a more substantial increase in velocity relative to relaxed Si.

The intrinsic performance and electron effective mobility of uniaxially strained-Si Gate-All-Around (GAA) NanoWire (NW) n-MOSFETs are investigated, for the first time. Suspended strained-Si NWs show very high stress (up to ~2.1GPA) as confirmed by Raman, with no bending of the wires. GAA strained-Si NW n-MOSFETs exhibit excellent subthreshold swing, and current drive and transconductance enhancement of ~2X over unstrained Si control NW devices. The mobility enhancement of these devices over unstrained planar and GAA MOSFETs as well as their scalability to circular NWs with radius of ~4 nm are also demonstrated.