Gate-All-Around n-MOSFETs With Uniaxial Tensile Strain-Induced Performance Enhancement Scalable to Sub-10-nm Nanowire Diameter

Abstract

The effects of high-level uniaxial tensile strain on the performance of gate-all-around (GAA) Si n-MOSFETs are investigated for nanowire (NW) diameters down to 8 nm. Suspended strained-Si NWs with ∼2-GPa uniaxial tension were realized by nanopatterning-induced unilateral relaxation of ultrathin-body 30% strained-Si-directly-on-insulator substrates. Based on these NWs, GAA strained-Si n-MOSFETs were fabricated with a Si thickness of ∼8 nm and NW widths in the range of 50 nm down to 8 nm. The GAA strained-Si MOSFETs show excellent subthreshold swing and cutoff behavior, and approximately two times current drive and intrinsic transconductance enhancement compared to similar unstrained Si devices.

Top-down fabricated silicon nanowires under tensile elastic strain up to 4.5%

“…A feasible approach would be, for example, to employ the well-established gate-all-around architeture 10,21 . In order to realize this design, we propose employing a gate last process in order to avoid strain relaxation, where activation of source and drain is performed before patterning, and where low temperature conformal deposition of high-κ gate oxide and metal gate is achieved using atomic layer deposition 22 .…”

“…Recently, silicon NWs with high uniaxial stress of ~2 GPa (~1.2% strain) have been demonstrated by patterning suspended NWs on highly strained silicon on insulator (SSOI) 10 . These substrates are fabricated by transferring the strained silicon layer from a virtual substrate to an oxidized silicon handle wafer via wafer bonding 11 .…”

“…The NWs patterned on highly strained silicon layers are released from the buried SiO 2 by wet chemical etching, relaxing the free surfaces while preserving the initial longitudinal strain. Up to two times enhancement in transconductance has been reported for transistors built with such highly strained NWs in respect to those made on conventional silicon substrate 10 .…”

Effects of forming gas anneal on ultrathin InGaAs nanowire metal-oxide-semiconductor field-effect transistors

“…The most possible reason is that the ohmic contact of the devices with FGA is worse than those without FGA, which can in turn increase on-state variation. To confirm this hypothesis, external resistance (R ext ) is extracted by linear fitting R tot and 1/(V gs -V t -V ds /2) at small V ds [17]. As shown in Figure 4 The results show that the InGaAs GAA MOSFETs with extremely thin T NW offer better immunity to SCE and improved scalability which can be further improved by equivalent oxide thickness (EOT) scaling [4,18,19].…”

Multigate Buckled Self-Aligned Dual Si Nanowire MOSFETs on Bulk Si for High Electron Mobility

“…7-9 are extracted and estimated using the y-intercept of total resistance (R tot = V DS /I D ) versus 1/(V GS − V TH − V DS /2) at V DS = 50 mV [28], assuming series resistance as the major transconductance drop mechanism in strong inversion regime. Note that the contribution of intrinsic mobility attenuation factor (θ 0 , see [24], can be influenced mainly by channel-dielectric interface quality [29]) on the transconductance drop in strong inversion should be negligible due to having an excellent gate stack (optimum subthreshold slope and pretty low leakage drain current in a sub-100 fA range for all the multi-gate devices at V DS = 50 mV).…”