Device optimization of bulk FinFETs and its comparison with SOI FinFETs

Manoj, C.R.; Meenakshi, N.; Dhanya, V.; Rao, V. Ramgopal

doi:10.1109/iwpsd.2007.4472472

Cited by 10 publications

(6 citation statements)

References 7 publications

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“…3 displays I ds -V ds characteristics of bulk FinFET at V gs = 0.6 V, 0.8 V, 1.0 V. By calibrating the parameters, the characteristics of bulk FinFET in the simulation can be well consistent with the experimental data in Ref. [11]. 2.5T10 -4…”

Section: Resultsmentioning

confidence: 54%

“…[9]- [13]. Since bulk FinFET has the disadvantage in sub channel leakage due to short channel lengths, [11] we need to consider the substrate leakage issues, which are important for reducing the power consumption and improving the device performance. The decreasing of the substrate leakage current can be achieved by modulating the substrate bias voltage.…”

Section: Introductionmentioning

confidence: 99%

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Three-dimensional Monte Carlo simulation of bulk fin field effect transistor

Wang¹,

Du²,

Wei³

et al. 2012

Chinese Phys. B

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In this paper, we investigate the performance of the bulk fin field effect transistor (FinFET) through a threedimensional (3D) full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO 2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.

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Section: Resultsmentioning

confidence: 54%

Section: Introductionmentioning

confidence: 99%

Three-dimensional Monte Carlo simulation of bulk fin field effect transistor

Wang¹,

Du²,

Wei³

et al. 2012

Chinese Phys. B

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“…FinFETs also present relative immunity to gate line-edge roughness, a major source of variability in planar nanoscale FETs (KING, 2005). The disadvantage over MOSFETs is the harder manufacturing process due to difficulty in the lithography steps as it is increasingly difficult to print small patterns, the increased variability impact due to the further minituarization of dimensions, in comparison to MOS-FET and more constly manufacturing process due to the need of techniques to address the manufacturing imprecision and, in the case of SOI FinFET, to change the CMOS substrate process to support a SOI substrate manufacturing process (KING, 2005) (MANOJ et al, 2007.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of variability using Schmitt trigger on full adders layout

Moraes

Zimpeck

Meinhardt

et al. 2018

Microelectronics Reliability

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The aggressive technology and voltage scaling which CMOS-based modern digital circuits are facing introduce challenges as short-channel effects, higher radiation and variability impact. As CMOS technology approaches its scaling limit, novel technology nodes, as FinFET, emerged to address such challenges. Although, even when shortchannel and radiation effects are mitigated due to technology instrinsic characteristics, the variability impact escalates with technology scaling and the lack of manufacturing precision. To mitigate that, novel techniques are proposed and tested in the literature. This work analyzes the impact on variability robustness using a technique based on the replacement of full adders internal inverters by Schmitt Triggers. Some works point that the given technique helps to improve the variability robustness at the electrical level. Therefore, analysis has been performed at layout level using the 7nm FinFET technology node from ASAP7 library and the technique was applied on four full adder designs. Performance, energy and area are taken into account. Results show up to 65% improvement on average delay and energy variability robustness, being necessary a trade-off analysis between robustness improvements and the impact on delays, power consumption and area.

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“…FinFET is also divided into bulk FinFET and SOI FinFET. Bulk FinFET is designed with high doping and have disadvantage of SCE for short channel length [9]. Therefore silicon on insulator FinFET is largely preferred.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET

Sikarwar

Khandelwal

Akashe

2013

2013 Third International Conference on Advanced Computing and Communication Technologies (ACCT)

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Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short channel effects, double gate FinFET is used. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. In this paper, six transistors SRAM cell is designed using the tied gate DG FinFET. Subthreshold leakage current and gate leakage current of internal transistors are observed and compared with the conventional structure of 6T SRAM cell. DG FinFET SRAM cell is applied with self controllable voltage level technique and then leakage current is observed. Simulation is performed with cadence virtuoso tool in 45 nm technology. The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique.

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Device optimization of bulk FinFETs and its comparison with SOI FinFETs

Cited by 10 publications

References 7 publications

Three-dimensional Monte Carlo simulation of bulk fin field effect transistor

Three-dimensional Monte Carlo simulation of bulk fin field effect transistor

Evaluation of variability using Schmitt trigger on full adders layout

Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET

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