The various analysis are established more on arithmetic circuits particularly with MUX design, this paper also explores with multiplexer to optimize the power. The CMOS transmission gate logic (TGL) is used to design a new 4:1 MUX with reduction in circuit complexity compared to conventional CMOS based multiplexer design. Based on TGL, it removes the degraded output, the NMOS and PMOS are combined together for strong output level with the gain in area, which is a central result of proposed MUX. The designed circuit is realized in 45 nm technology, with the power dissipation of 1.887 nW from a 0.7 V supply voltage. The MUX can operate well up to 200 Gb/s.
In the design of high performance complex arithmetic logic circuits, ground bounce noise, leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, the low power and reduced ground bounce noise using 10 transistor full adder has been proposed. Full adder is the most important basic building of digital circuits employing arithmetic operation. Adder circuit is widely used in many digital circuits not only for arithmetic operation but also for address generation in processors and microcontrollers. It is therefore necessary to make these systems more e±cient so that they consume less power. Here, we use stacking power gating technique to evaluate leakage current, power and ground bounce noise. This paper describes reduction of leakage power and ground bounce noise from the 10 T full adder circuits to make it more reliable to be used to have low power and stable and errorless output. All the simulation in this paper has been carried out using cadence virtuoso at 45 nm technology at various voltages and various temperatures. By using this technique the leakage current reduction can be improved by 80% and leakage power to 70% as compared to conventional 10 T full adder. Ground bounce noise can be reduced to 60% as compared to the base full adder.
Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short channel effects, double gate FinFET is used. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. In this paper, six transistors SRAM cell is designed using the tied gate DG FinFET. Subthreshold leakage current and gate leakage current of internal transistors are observed and compared with the conventional structure of 6T SRAM cell. DG FinFET SRAM cell is applied with self controllable voltage level technique and then leakage current is observed. Simulation is performed with cadence virtuoso tool in 45 nm technology. The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.