The various analysis are established more on arithmetic circuits particularly with MUX design, this paper also explores with multiplexer to optimize the power. The CMOS transmission gate logic (TGL) is used to design a new 4:1 MUX with reduction in circuit complexity compared to conventional CMOS based multiplexer design. Based on TGL, it removes the degraded output, the NMOS and PMOS are combined together for strong output level with the gain in area, which is a central result of proposed MUX. The designed circuit is realized in 45 nm technology, with the power dissipation of 1.887 nW from a 0.7 V supply voltage. The MUX can operate well up to 200 Gb/s.
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