Abstract-The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I on . We propose the use of high-κ spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si 3 N 4 spacers, with κ = 20 spacers, we show that it is possible to achieve an 80% increase in I on at iso-I off conditions and a 15% decrease in the inverter delay for a fan-out of four.Index Terms-CMOS scaling, FinFET, fringe-induced barrier lowering (GFIBL), high-κ materials, short-channel effects (SCEs).

The impact of high-k gate dielectrics on device shortchannel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C of in addition to an increase in the internal fringe capacitance C if with high-k dielectrics, which degrades the shortchannel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering.Index Terms-Fin field-effect transistors (FinFETs), fringinginduced barrier lowering (FIBL), high-k gate dielectric, noise margin, short-channel effects (SCEs).

Abstract-Fabrication of FinFETs using bulk CMOS instead of silicon on insulator (SOI) technology is of utmost interest as it reduces the process costs. Using well-calibrated device models and 3-D mixed mode simulations, we show that bulk FinFETs can be optimized with identical performances as that of SOI FinFETs. Optimized bulk FinFETs are compared with the corresponding SOI FinFETs for a range of technology nodes using an extensive simulation and design methodology. Further, we extend the concept of body doping in bulk FinFETs to the case of lightly doped fins unlike the heavily doped fin cases reported earlier. The optimum body doping required for bulk FinFETs, and its multiple advantages are also systematically evaluated. We also show that device parasitics play a crucial role in the optimization of nanoscale bulk FinFETs.

In this letter, we report the enhanced fringe capacitance in FinFETs when compared to the equivalent planar MOSFETs at the 22-nm node. We show that this increase is due to the 3-D nature of the device and also due to the close proximity of the source/drain (S/D) epitaxial (epi) region to the metal gate. Using well-calibrated 3-D mixed-mode simulations, we show that this will cause the performance of FinFETs to be significantly degraded, unless proper device optimizations are carried out. Our results also indicate that the selective epi growth of S/D may adversely affect the overall performance of FinFETs, although it is effective in reducing series resistance. The increased parasitic components in FinFETs can be a serious issue for FinFET circuits with a large fan-out, and the solution lies in the aggressive fin pitch reduction, as shown in this letter.

Abstract-In this paper, a comprehensive study of hotcarrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: 1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; 2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and 3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement.Index Terms-Germanium, high-k, hot carrier (HC), impact ionization, negative bias temperature instability (NBTI), pMOSFET.