Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs

Manoj, C.R.; Sachid, Angada B.; Yuan, Feng; Chang, Chang-Yun; Rao, V. Ramgopal

doi:10.1109/led.2009.2035934

Cited by 29 publications

(14 citation statements)

References 9 publications

(8 reference statements)

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“…UTB-SOI MOSFETs have a higher access resistance than FinFETs, a major fraction of which is from the contact resistance due to the lower contact area [27]. On the other hand, FinFETs have a higher outer fringe capacitance compared to UTB-SOI MOSFETs due to the 3D nature of the device [28]. By reducing the fin pitch to 80 nm, it is possible to reduce the outer fringe capacitance and make it equal to that of UTB-SOI MOSFET device.…”

Section: Comparison Between Technologiesmentioning

confidence: 99%

Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework

Sachid

Thakker

Sathe

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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In this paper, we present Auto-BET-AMS, an automated device, circuit and system-level simulation platform suitable for benchmarking emerging technologies at the end of the CMOS roadmap. This platform is suitable for technologists and circuit designers alike. One of the features of Auto-BET-AMS is that no advanced knowledge of device and circuit design is needed to perform a fair evaluation of emerging technologies. To enable this, the platform comes with a versatile multi-variable optimizer that can be used to quickly optimize devices and circuits for a set of specifications. Using Auto-BET-AMS it is possible to accurately design digital and analog circuits and assess them in conventional and emerging technologies. The platform can handle definitions of chargebased devices in either the compact model form or a look-up table form. The latter is needed for devices which do not have mature compact models developed for them. Several representative digital and analog circuits like buffer chain, SRAM cell, two-stage Miller Op-Amp, three-stage lowvoltage Op-Amp, temperature compensated current reference and Miller OTA are optimized by considering PVT variations using Auto-BET-AMS. Additionally, the impact of parametric variations on these circuits is studied. IntroductionAt the end of the CMOS roadmap, a large number of interesting device concepts like UTB-SOI MOSFET [1], Schottky-Barrier MOSFET [2], Tunnel FET [3], FinFET [4] etc, have emerged as possible alternatives for the mainstream bulk MOSFET technology. Among these devices, UTB-SOI MOSFET and FinFET devices are promising. A fair comparison between various technologies at the device, circuit and system-level is essential in order to assess the true potential of these technologies. For this, not only parasitics at the device level but also the impact of interconnects and parametric variability should be included. Technology development is a highly iterative process which involves tweaking a combination of the device characteristics, circuits and architecture design. With multiple competing technology choices at the lower technology nodes, it is essential to have a fast, accurate and efficient platform to benchmark emerging technologies.Technology CAD (TCAD) is used extensively for device optimization. Essentially a TCAD tool predicts the performance of devices by solving the Poisson and continuity equations using a set of boundary conditions. TCAD is also capable of predicting the behavior and performance of circuits. Circuit simulations using TCAD are time consuming as it has to solve simultaneous device equations for all the devices in the circuit. On the other hand, circuit simulation using compact models is time-efficient and has been used extensively for circuit design and optimization. In dedicated

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Section: Comparison Between Technologiesmentioning

confidence: 99%

Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework

Sachid

Thakker

Sathe

et al. 2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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“…Advantages of FinFETs over conventional planar MOSFETs are high immunity to short-channel effects, drain-induced barrier lowering, high gate controllability, and reduction of leakage current [2][3][4]. Although FinFETs are potentially advantageous for further scaling, parasitic components present an important obstacle: fringing capacitances increase with scaling due to the increasing proximity of the source/drain selective epitaxial growth (SEG) region [5] and of the massive contact with a short length of interconnect to the gate [6], and series resistance also increases as the width of the fins is narrowed [7,8]. These parasitics degrade circuit-level performance metrics such as digital circuit delay and analog/RF performance [6].…”

Section: Introductionmentioning

confidence: 99%

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

An¹,

Choe²,

Kwon³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (f T ). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.Index Terms-Cutoff frequency, fin field-effect transistors (FinFETs), fringe capacitance, number of gate fingers, number of fins, parasitic resistance, radio frequency (RF).

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“…The essential idea behind these MOSFET structures is to allow the gate electrode to have better control of the electric potential of the MOSFET channel such that both a high turn-on driving current and an extremely low tum-off leakage current may be obtained. When used for high-frequency applications however, these MOSFET structures may exhibit serious shortcomings due to the associated parasitic capacitances and resistances [2]. Recent research works in the literature have reported high performance MOSFET structures of nanometre scale.…”

Section: Introductionmentioning

confidence: 99%

Impact of parasitic elements on RF performance of nanometre-scale MOSFET structures

Lam

2013

2013 IEEE International Conference of Electron Devices and Solid-State Circuits

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A recently reported nanometre-scaled MOSFET structure with regrown source and drain is examined. The parasitic circuit elements are identified and quantitatively determined to estimate their impact on the transistor's RF performance. Due to the relatively large lateral parasitic capacitances from the gate electrode to the regrown source and drain regions, the current gain cut-off frequency fT of such a transistor is optimistically estimated to be 184 GHz which is not impressive for nanoelectronic devices with an effective gate length of 30 nm. However, with the significantly reduced parasitic series resistances due to the regrown source and drain structures together with the use of the metal gate, the maximum frequency of oscillation fmax can attain to 820 GHz. This brings about an implication that device structure optimization to reduce the parasitic resistances has a dominant beneficial effect on the RF performance over the negative impact caused by the increased parasitic capacitances.

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Impact of Fringe Capacitance on the Performance of Nanoscale FinFETs

Cited by 29 publications

References 9 publications

Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework

Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

Impact of parasitic elements on RF performance of nanometre-scale MOSFET structures

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