Abstract-In this paper, we investigate the quality of MOSFET gate stacks where high-k materials are implemented as gate dielectrics. We evaluate both drain-and gate-current noises in order to obtain information about the defect content of the gate stack. We analyze how the overall quality of the gate stack depends on the kind of high-k material, on the interfacial layer thickness, on the kind of gate electrode material, on the strain engineering, and on the substrate type. This comprehensive study allows us to understand which issues need to be addressed in order to achieve improved quality of the gate stack from a 1/f noise point of view.Index Terms-Drain noise, gate noise, high-k dielectric, MOSFET, 1/f noise.

In this work we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in a one sub-band approximation and carrier degeneracy. The knowledge of the barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time we obtain also an estimate of the backscattering ratio and of the saturation inversion charge. Respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction method is fully consistent with it, whereas other methods make a number of approximations in the calculation of the saturation inversion charge which are inconsistent with the model. The proposed experimental extraction method has been validated and applied to results from device simulation and measurements on short-channel poly-Si/SiON gate nMOSFETs with gate length down to 70 nm. Moreover we propose an extension of the backscattering model to the case of 2D geometries (e.g. bulk MOSFETs). We found that, in this case, the backscattering is governed by the carrier transport in a few nanometers close to the silicon/oxide interface and that the value of the backscattering ratio obtained with a 1D approach can be significantly different from the real 2D value

Articles you may be interested inCharge trapping induced drain-induced-barrier-lowering in HfO2/TiN p-channel metal-oxide-semiconductor-fieldeffect-transistors under hot carrier stress Appl. Phys. Lett. 100, 152102 (2012); 10.1063/1.3697644Hf O 2 -based InP n -channel metal-oxide-semiconductor field-effect transistors and metal-oxide-semiconductor capacitors using a germanium interfacial passivation layer

Abstract-In this paper, a comprehensive study of hotcarrier injection (HCI) has been performed on high-performance Si-passivated pMOSFETs with high-k metal gate fabricated on n-type germanium-on-silicon (Ge-on-Si) substrates. Negative bias temperature instability (NBTI) has also been explored on the same devices. The following are found: 1) Impact ionization rate in Ge-on-Si MOSFETs is approximately two orders higher as compared to their Si counterpart; 2) NBTI degradation is a lesser concern than HCI for Ge-on-Si pMOSFETs; and 3) increasing the Si-passivation thickness from four to eight monolayers provides a remarkable lifetime improvement.Index Terms-Germanium, high-k, hot carrier (HC), impact ionization, negative bias temperature instability (NBTI), pMOSFET.

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