Gate Fringe-Induced Barrier Lowering in Underlap FinFET Structures and Its Optimization

Abstract

Abstract-The difficulty to fabricate and control precisely defined doping profiles in the source/drain underlap regions of FinFETs necessitates the use of undoped gate underlap regions as the technology scales down. We present a phenomenon called the gate fringe-induced barrier lowering (GFIBL) in FinFETs with undoped underlap regions. In these FinFETs, we show that the GFIBL can be effectively used to improve I on . We propose the use of high-κ spacers in such FinFETs to enhance the effect of GFIBL and thereby achieve better device and circuit performance. When compared with the underlap FinFETs with Si 3 N 4 spacers, with κ = 20 spacers, we show that it is possible to achieve an 80% increase in I on at iso-I off conditions and a 15% decrease in the inverter delay for a fan-out of four.Index Terms-CMOS scaling, FinFET, fringe-induced barrier lowering (GFIBL), high-κ materials, short-channel effects (SCEs).

Exploration of symmetric high-k spacer (SHS) hybrid FinFET for high performance application

“…In this work, we have incorporated the symmetric high-k spacer (SHS) in the underlap regions near S/D side of the hybrid FinFET. Previously, the underlap FinFETs have already earned very good control over SCEs [13,14]. Similarly, Pal et al [1,2] have proposed that excellent control over channel and significant improvement in I on and I off are achievable with contemplate dual-k spacers in the underlap region.…”

Impact of dual-k spacer on analog performance of underlap FinFET

“…Gate fringe induced barrier lowering (GFIBL) is observed in undoped underlap FinFETs with an increase in the dielectric constant of spacer region (L ext ) [12]. The barrier to lateral drain electric field is lowered in strong inversion because of increase in the coupling of gate fringing fields to undoped underlap portion of FinFET.…”

“…Therefore, analysis is carried out at 8 nm of fin thickness (T fin ). High dielectric (High-k) spacers in underlap FinFET are reported to modulate the barrier in undoped underlap length of FinFETs [12]. The barrier modulation is a direct consequence of increase in gate fringing field which shifts the lateral electric field at the gate edge toward drain.…”

Dual-$V_{th}$ Independent-Gate FinFETs for Low Power Logic Circuits

“…The 2-D FinFET structure shown in Fig. 1 [25] was used for the simulations. In Sentaurus, the drift-diffusion mobility and density-gradient quantum correction models were enabled.…”