Abstract-Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper we investigate the critical charge (Q crit ) required to upset a 6T SRAM cell designed in a commercial 90nm process. We characterize Q crit using different current models and show that there are significant differences in Q crit values depending on which models are used. Discrepancies in critical charge characterization are shown to result in under-predictions of the SRAM's associated soft error rate as large as two orders of magnitude. For accurate Q crit calculation, it is critical that 3D device simulation is used to calibrate the current pulse modeling heavy ion strikes on the circuit, since the stimuli characteristics are technology feature size dependant. Current models with very fast characteristic timing parameters are shown to result in conservative soft error rate predictions; and can assertively be used to model ion strikes when 3D simulation data is not available.

Hysteretic switching with a sub-kT/q steep slope (13 mV/decade at room temperature) is experimentally demonstrated in MOSFETs with PbZr 0.52 Ti 0.48 O 3 as a ferroelectric (FE) gate insulator, integrated on a silicon channel with a nonperovskite high-k dielectric (HfO 2 ) as a buffer interlayer. The steep switching is independent of drain bias. For the first time, sub-kT/q switching due to FE negative capacitance is observed not at low currents, but in strong inversion (I d ∼ 100 µA/µm). Steep switching in strong inversion provides an important point of consistency with the predictions of the Landau-Devonshire theory and the Landau-Khalatnikov equation. INDEX TERMSFerroelectric (FE) field-effect transistor (FET), lead zirconate titanate, negative capacitance (NC), sub-kT/q switching.

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