Evaluation of variability using Schmitt trigger on full adders layout

Abstract

The aggressive technology and voltage scaling which CMOS-based modern digital circuits are facing introduce challenges as short-channel effects, higher radiation and variability impact. As CMOS technology approaches its scaling limit, novel technology nodes, as FinFET, emerged to address such challenges. Although, even when shortchannel and radiation effects are mitigated due to technology instrinsic characteristics, the variability impact escalates with technology scaling and the lack of manufacturing precision. To mitigate that, novel techniques are proposed and tested in the literature. This work analyzes the impact on variability robustness using a technique based on the replacement of full adders internal inverters by Schmitt Triggers. Some works point that the given technique helps to improve the variability robustness at the electrical level. Therefore, analysis has been performed at layout level using the 7nm FinFET technology node from ASAP7 library and the technique was applied on four full adder designs. Performance, energy and area are taken into account. Results show up to 65% improvement on average delay and energy variability robustness, being necessary a trade-off analysis between robustness improvements and the impact on delays, power consumption and area.

Mitigation of process variability effects using decoupling cells

“…This work showed an overview of the use of decoupling cells in FinFET logic gates for process variability mitigation. Among all methods presented in the literature [5][6][7][8][9], the insertion of decoupling cells had the best improvement in the normalized standard deviation (σ/µ), and lower penalties in area, power, and performance. For these reasons, this technique can be considered favorable to attenuate the process variability impact, mainly when the logic gates suffer process deviation above 4% on the metal gate work-function.…”

“…To the best of our knowledge, few works are evaluating the influence of process variations at layout level in FinFET technologies as well as proposing or evaluating techniques to deal with process variations issues. In general, the approaches employed in the literature to mitigate the effects of process variations are focusing on the usage of different structure or material during the fabrication process [5,6], the replacement of traditional inverters by Schmitt Triggers in full-adders [7], the adoption of multilevel version instead of complex gates [8] or the transistor arrangements reordering [9].…”

Circuit design using Schmitt Trigger to reliability improvement

“…To the best of our knowledge, only a few works are focusing on circuit-level methods for increasing the robustness of FinFET circuits to soft errors and process variability [15][16][17][18][19]. A dual-interlocked logic demonstrates to be resilient to SET impact for even for dual-node strikes using a 14nm FinFET technology [15].…”

“…The multilevel design instead of complex cells was studied in [17] as a mitigation strategy using the 7nm FinFET technology. The replacement of traditional inverters by Schmitt Triggers significantly decreases the process variability sensitivity in FinFET full adders designed in 7nm FinFET node [18]. The SET robustness due to the low-pass filter and redundancy strategies was explored in [19], adopting a 10nm FinFET node.…”

Sleep Transistors to Improve the Process Variability and Soft Error Susceptibility

“…Some related works investigate the replacement of traditional inverts by Schmitt Triggers in FinFET full-adders showing up to be 37% more robust to the process variability impact [7]. Also, the concept of strengthening was applied in a FinFET inverter and compared with classical methods.…”