All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths

Abstract

Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18um CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB.

A Novel Low Power, Minimal Dead Zone Digital PFD for Biomedical Applications

“…Time to Amplitude Converter TDC (TACTDC) [7], is the combination of TAC and ADC (Analog to Digital Converter), the entire operation depends on the charging mechanism of a capacitor on the output section of the TAC. The capacitor value is then converted into a digital value with the help of ADC.…”

“…The capacitor value is then converted into a digital value with the help of ADC. Very simple to implement is the major advantage for ASICs, but they have a large dead time and the limited resolution for ADC operation, a high power dissipation for 50 ps resolution [7]. Because of its complete analogy in its structure designing, it has no CMOS implementation.…”

“…Vernier Delay Line TDC (VDLTDC) [6,7] can measure the delay line with sub gate resolution mechanism. This architecture delays both START and STOP signals with uneven time periods (delay of STOP signal is slightly greater than the START signal) which is the START signal that leads the STOP signal.…”

“…According to TDC's report, it drastically reduced the number of ADPLL converters required, but the remaining technical limitations were severely affected [3][4][5][6][7]. These results make TDC based ADPLLs were not suitable for biomedical applications, but ADPLLs are the major functional unit in BIMDs, and there is a need for significant improvement in this area.…”

“…For detailed information on, How ADPLLs subtle the PLLs & Digital PLLs (DPLLs)? block diagram of PLL, categories of DPLLs, reader has suggested to read [3][4][5][6][7][8].…”