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Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18um CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB.

This paper presents a TDC architecture based on a gray code oscillator with improved linearity, for FPGA implementations. The proposed architecture introduces manual routing as a method to improve the TDC linearity and precision, by controlling the gray code oscillator Datapath, which also reduces the need for calibration mechanisms. Furthermore, the proposed manual routing procedure improves the performance homogeneity across multiple TDC channels, enabling the use of the same calibration module across multiple channels, if further improved precision is required. The proposed TDC channel uses only 16 FPGA logic resources (considering the Xilinx 7 series platform), making it suitable for applications where a large number of measurement channels are required. To validate the proposed architecture and routing procedure, two channels were integrated with a coarse counter, a FIFO memory and an AXI interface, to assemble the pulse measurement unit. A comparison between the default routing implementation and the proposed manual routing has been performed, shown an improvement of 27% on the overall TDC single-shot precision. The implemented TDC achieved a 380 ps RMS resolution, a maximum DNL of 0.38 LSB and a peak-to-peak INL of 0.69 LSB, corresponding to a 21.7% and 70.4% improvement, respectively, when compared to the default design approach.

In recent years there has been an increase in the number of research and developments in deep learning solutions for object detection applied to driverless vehicles. This application benefited from the growing trend felt in innovative perception solutions, such as LiDAR sensors. Currently, this is the preferred device to accomplish those tasks in autonomous vehicles. There is a broad variety of research works on models based on point clouds, standing out for being efficient and robust in their intended tasks, but they are also characterized by requiring point cloud processing times greater than the minimum required, given the risky nature of the application. This research work aims to provide a design and implementation of a hardware IP optimized for computing convolutions, rectified linear unit (ReLU), padding, and max pooling. This engine was designed to enable the configuration of features such as varying the size of the feature map, filter size, stride, number of inputs, number of filters, and the number of hardware resources required for a specific convolution. Performance results show that by resorting to parallelism and quantization approach, the proposed solution could reduce the amount of logical FPGA resources by 40 to 50%, enhancing the processing time by 50% while maintaining the deep learning operation accuracy.

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Due to a point cloud’s sparse nature, a sparse convolution block design is necessary to deal with its particularities. Mechanisms adopted in computer vision have recently explored the advantages of data processing in more energy-efficient hardware, such as the FPGA, as a response to the need to run these algorithms on resource-constrained edge devices. However, implementing it in hardware has not been properly explored, resulting in a small number of studies aimed at analyzing the potential of sparse convolutions and their efficiency on resource-constrained hardware platforms. This article presents the design of a customizable hardware block for the voting convolution. We carried out an in-depth analysis to determine under which conditions the use of the voting scheme is justified instead of dense convolutions. The proposed hardware design achieves an energy consumption about 8.7 times lower than similar works in the literature by ignoring unnecessary arithmetic operations with null weights and leveraging data dependency. Access to data memory was also reduced to the minimum necessary, leading to improvements of around 55% in processing time. To evaluate both the performance and applicability of the proposed solution, the voting convolution was integrated into the well-known PointPillars model, where it achieves improvements between 23.05% and 80.44% without a significant effect on detection performance.

This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL's steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied.

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