Technology Independent ASIC Based Time to Digital Converter

Abstract

This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL's steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied.

A massively scalable Time-to-Digital Converter with a PLL-free calibration system in a commercial 130 nm process

“…Solutions [11,15,16] and [17] are characterized by smaller power consumption and LSB but they have been developed in a more advanced technological node and, as explained in section 1, the complexity and/or the limited maximum measurable time interval make them more difficult to be integrated in large pixel detector chips. The non-linearities of the presented -18 -2021 JINST 16 P11023 1 and the ones reported in [24][25][26][27][28][29][30][31][32][33][34][35][36]. The size of the dots on the plot is proportional to the power consumption of the analyzed TDCs (logarithmic scale).…”

“…Figure20. Area and LSB of the presented TDC compared to the works of table 1 and the ones reported in[24][25][26][27][28][29][30][31][32][33][34][35][36]. The size of the dots on the plot is proportional to the power consumption of the analyzed TDCs (logarithmic scale).…”