This presents an all-digital phase-locked loop (ADPLL) system using triple-stage phaseshifting (TSPS) for fast locking. At the first stage, a phase-pulling multiplexer linearly pulls the phase of a feedback signal until the phase offset between the feedback and reference signals becomes sufficiently small. Then, a toggling phase-shifting in the second stage achieves further reduction of the phase offset by delaying the feedback and reference signals. A subsequent adaptive target index-shifting stage then detects fine-locking in frequency and rapidly performs phase-locking to the present phase of the feedback signal instead of the initial target phase. This TSPS-ADPLL avoids frequency peaking by choosing oscillator control codes that generate frequencies below or near the target. Fabricated in a 28nm CMOS process, this ADPLL can lock within 1.0s, producing a 2.4GHz output clock without frequency peaking. It has an RMS jitter of 2.53ps and draws 2.89mW from a 1.0V supply.INDEX TERMS Fast-locking, phase-shifting, frequency peaking, frequency search, digital clock generator, all-digital phase-locked loop (ADPLL).
This work presents a low-power and fast-locking digital 1.6GHz quadrature clock generator (QCG), which mainly consists of a novel ping-pong phase detection (PPD) controller with a pair of latch-based phase detectors. The proposed PPD scheme compares generated clock signals from a digitally controlled delay line (DCDL) with an input clock for fast coarse lock, resulting in a short locking time. Post-layout simulations of an implementation in 28nm CMOS technology suggest that the proposed work can lock within 13 cycles and produce 4-phase 1.6GHz quality output clocks, which supports a data rate of 6.4Gbps. It achieves an RMS jitter of 1.65ps and an effective peak-to-peak jitter of 1.12ps, offers power efficiency of 0.25mW/Gbps, and occupies an area of 0.00247mm 2 .
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