This paper presents a new Distributed Linear VoltageRegulator designed to supply large CMOS cores at multiple points. The new embedded regulator has been designed with distributed power devices in order to reduce the supply routing constraints of large integrated cores. The regulator has been optimised to regulate a very wide load range with large current transients without requiring large filter capacitors nor compromising its low quiescent current (150 uA) The regulator was fabricated in a 0 . 2 5~ standard digital CMOS process, occupies 0.15mm2 and can supply 400mA of load at 2.5V from a 3.3V supply. Four supply points are used. Furthermore, a very compact chip area is achieved due to a modified Miller compensation network that guarantees stability at a fraction of the chip area of conventional compensation networks. This circuit is particularly suited for digital processing cores as well as other processing cores requiring hundreds of milliamp of current.
This paper proposes a design methodology for a synthesizable, fully digital TDC architecture. The TDC was implemented using a hardware description language (HDL), which improves portability between platforms and technologies and significantly reduces design time. The proposed design flow is fully automated using TCL scripting and standard CAD tools configuration files. The TDC is based on a Tapped Delay Line architecture and explores the use of Structured Data Path (SDP) as a way to improve the TDL linearity by homogenizing the routing and parasitic capacitances across the multiple TDL's steps. The studied approach also secures a stable, temperature independent measurement operation. The proposed TDC architecture was fabricated using TSMC 180nm CMOS process technology, with a 50MHz reference clock and a supply voltage of 1.8V. The fabricated TDC achieved an 111ps RMS resolution and a single-shot precision of 54ps (0.48 LSB) and 279ps (2.51 LSB), with and without post-measurement software calibration, respectively. The DNL across the channel is mostly under 0.3 LSB and a maximum of 8 LSB peak-to-peak INL was achieved, when no calibration is applied.
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