A 0.25–1.0 V fully synthesizable three-stage dynamic voltage comparator based XOR&amp;XNOR&amp;NAND&amp;NOR logic

Zhou, Ting; Li, Xiaocui; Ji, Yingchun; Li, Yongfu

doi:10.1007/s10470-021-01838-7

Cited by 6 publications

(3 citation statements)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Also, the PDP is more unstable when the temperature is above room temperature. Hence, the best conduction temperature of the design is around or below room temperature [10].…”

Section: Resultsmentioning

confidence: 99%

Review of Four Improving Designs of Dynamic Latch Comparator

Wang¹

2023

HSET

View full text Add to dashboard Cite

In this paper, four disparate designs of dynamic latch comparators are discussed consecutively. By improving the design of the pre-amplifier stage, the double tail comparator provides a good power-speed trade-off. Further, Differential pair amplifiers are implemented in the second design, which has better comparison speed and energy dissipation. Next, a bulk-driven structure is employed on the comparator design to improve the comparison speed. Finally, a dynamic comparator utilizes a floating reservoir capacitor and a positive feedback bulk structure is introduced to achieve higher energy efficiency. The overall performance of these comparators is evaluated in this paper.

show abstract

“…Also, the PDP is more unstable when the temperature is above room temperature. Hence, the best conduction temperature of the design is around or below room temperature [10].…”

Section: Resultsmentioning

confidence: 99%

Review of Four Improving Designs of Dynamic Latch Comparator

Wang¹

2023

HSET

View full text Add to dashboard Cite

show abstract

“…The usual approach to design standard-cell-based latched comparators starts from a NAND-based [3,[6][7][8]46] or NOR-based latch [50,51], and several designs have been presented in the literature to optimize different performances for applications in ADCs and LDOs [9,10,49,[52][53][54][55][56][57]. However, such applications typically focus on different performance parameters, hence proposed designs are not always easy to compare.…”

Section: Introductionmentioning

confidence: 99%

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

Della Sala,

Centurelli,

Scotti

et al. 2023

Chips

View full text Add to dashboard Cite

This work is focused on the performance of three different standard-cell-based comparator topologies, considering ultra-low-voltage (ULV) operation. The main application scenarios in which standard-cell-based comparators can be exploited are considered, and a set of figures of merit (FoM) to allow an in-depth comparison among the different topologies is introduced. Then, a set of simulation testbenches are defined in order to simulate and compare the considered topologies implemented in both a 130 nm technology and a 28 nm FDSOI CMOS process. Propagation delay, power consumption and power–delay product are evaluated for different values of the input common mode voltage, as a function of input differential amplitude, and in different supply voltage and temperature conditions. Monte Carlo simulations to evaluate the input offset voltage under mismatch variations are also provided. Simulation results show that the performances of the different comparator topologies are strongly dependent on the input common mode voltage, and that the best values for all the performance figures of merit are achieved by the comparator based on three-input NAND gates, with the only limitation being its non-rail-to-rail input common mode range (ICMR). The performances of the considered comparator topologies have also been simulated for different values of the supply voltage, ranging from 0.3 V to 1.2 V, showing that, even if standard-cell-based comparators can be operated at higher supply voltages by scaling their performances accordingly, the best values of the FoMs are achieved for VDD = 0.3 V.

show abstract

“…The simplest latched comparator can be implemented using cross-coupled 3-input NAND gates [57]. This configuration provides a very compact comparator but with a limited ICMR, therefore, architectures that pair both NAND and NOR gates as input cells [36,[58][59][60], or are based on AND-OR-INVERTER (AOI) gates [61], have been proposed to achieve a rail-to-rail ICMR, at the cost of higher complexity and area footprint.…”

Section: Introductionmentioning

confidence: 99%

A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

Sala

Spinogatti

Bocciarelli

et al. 2023

JLPEA

View full text Add to dashboard Cite

In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.

show abstract

A 0.25–1.0 V fully synthesizable three-stage dynamic voltage comparator based XOR&XNOR&NAND&NOR logic

Cited by 6 publications

References 21 publications

Review of Four Improving Designs of Dynamic Latch Comparator

Review of Four Improving Designs of Dynamic Latch Comparator

Standard-Cell-Based Comparators for Ultra-Low Voltage Applications: Analysis and Comparisons

A 0.15-to-0.5 V Body-Driven Dynamic Comparator with Rail-to-Rail ICMR

Contact Info

Product

Resources

About