SummaryIn this paper, an evolution of the Sallen–Key biquad architecture is presented, suitable for applications at very high frequency. The pole of the buffer amplifier is exploited as one of the poles of the biquad, therefore overcoming the constraints it poses on the maximum resonance frequency that can be achieved. This allows designing low‐pass filters with cutoff frequencies above 10 GHz without using bulky inductors and with good linearity performance provided by the use of feedback. This approach has been exploited to design a biquad in a commercial SiGe BiCMOS technology with maximum
of about 320 GHz. The biquad has been designed to provide a resonance frequency
of 12 GHz and a quality factor Q of 1.9; postlayout simulations show a cutoff frequency in excess of 17 GHz, 15.75 mW of power consumption, an equivalent input noise below 1
Vrms, and −52 dB of total harmonic distortion (THD) for a 640 mVpp input signal, with a very limited area consumption.
Nonlinear calibration allows enhancing the performance of analog and radiofrequency circuits by digitally correcting nonlinearities. Often, calibration is performed in the complex baseband domain, and Volterra models are used. These models have hundreds of coefficients, and easily become computationally unfeasible. This is worse in complex Volterra models, because high-order Volterra terms require summing multiple products of the input signal. We propose a generalized complex Volterra model based on one relaxation of Volterra theory: all the nonlinear monomial terms in the model are considered separately, even if they correspond to a single real coefficient in complex Volterra theory. This produces more accurate models, though with a larger number of coefficients. We thus extensively prune the model by means of OMP and OBS techniques. The resulting models have fewer coefficients and/or better accuracy than conventional Volterra models, resulting in a significantly improved accuracy-complexity tradeoff. These results are validated in the experimental calibration of a commercial IF amplifier. The resulting model achieves the same accuracy, with 9 free parameters and 34 multiplications, as the standard Volterra model with 12 parameters and 266 multiplications, resulting in a 25% reduction in the number of parameters, and an 87% reduction in the number of multipliers.
In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. The simulations show that the comparator remains fully operational even when the supply voltage is scaled down to 0.15 V, in which case the circuit exhibits a maximum operating frequency of 80 kHz at Vid=1 mV.
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