Robust Body Biasing Techniques for Dynamic Comparators

Spinogatti, Valerio; Bocciarelli, Cristian; Centurelli, Francesco; Sala, R.; Trifiletti, Alessandro

doi:10.1109/prime58259.2023.10161788

Cited by 3 publications

(4 citation statements)

References 9 publications

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“…This causes the body voltage V bn to change due to charge redistribution. The charge redistribution phenomenon can be be analyzed by referring to the model shown in Figure 6 [26]. In the circuit, C 8 corresponds to the parallel parasitic capacitance associated with M 8 , while C bd and C bs represent the body-drain and body-source parasitic capacitances of M 3 -M 4 , respectively.…”

Section: Clocked Fbbmentioning

confidence: 99%

“…In [26], an improved version of CFBB was proposed in an attempt to overcome its limitations. The modified CFBB scheme, which is denominated hybrid FBB (HFBB), is shown in Figure 7.…”

Section: Hybrid Fbbmentioning

confidence: 99%

“…In [26], it was shown that CFBB can suffer from robustness issues when a large differential voltage is applied to the comparator's inputs. Moreover, CFBB is limited in that it cannot be applied to the PMOS devices of the latch, which limits the advantage associated with FBB.…”

Section: Introductionmentioning

confidence: 99%

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Body Biasing Techniques for Dynamic Comparators: A Systematic Survey

Spinogatti,

Della Sala,

Bocciarelli

et al. 2024

Electronics

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Forward body biasing (FBB) has often been exploited in the literature for improving the performance of both analog and digital building blocks. Recent works have explored the application of FBB variants to mixed-signal electronics and in particular to dynamic comparators, where these techniques can help to relax the trade-off between speed and power consumption at medium and low supply voltages. However, the literature lacks a structured analysis of the solutions that have been developed and of the trade-offs that affect them. This work attempts to fill the gap by providing a survey of the application of FBB techniques to dynamic comparators. The analysis focuses on the two most popular dynamic comparator topologies, the Strong Arm latch and Elzakker’s comparator. Several FBB variants are examined from a theoretical point of view. Moreover, the benefits and the limitations of the different approaches are assessed in terms of the main figures of merit through a systematic campaign of simulations in a 55 nm CMOS technology.

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Section: Clocked Fbbmentioning

confidence: 99%

“…In [26], an improved version of CFBB was proposed in an attempt to overcome its limitations. The modified CFBB scheme, which is denominated hybrid FBB (HFBB), is shown in Figure 7.…”

Section: Hybrid Fbbmentioning

confidence: 99%

See 1 more Smart Citation

Body Biasing Techniques for Dynamic Comparators: A Systematic Survey

Spinogatti,

Della Sala,

Bocciarelli

et al. 2024

Electronics

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“…Owing to such popularity, numerous efforts have been made in the literature with the intent of further improving the performance of this topology. Numerous proposals focus on relaxing the trade-off between speed and power consumption: in [1], [5], for instance, forward bodybias (FBB) is exploited to improve speed with a negligible increase in power consumption. The authors of [6] propose to modify the topology so that a pair of reset devices can be removed, which results in smaller delay and power consumption.…”

Section: Introductionmentioning

confidence: 99%

An Improved Strong Arm Comparator With Integrated Static Preamplifier

Spinogatti,

Sala,

Bocciarelli

et al. 2023

IEEE Access

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This paper presents a novel Strong Arm comparator in which the input pair is reused as a static amplifier to preamplify the input signal during the precharge phase. The proposed approach relaxes the main trade-offs that characterize the Strong Arm latch: compared to the conventional topology, the enhanced comparator achieves better input-referred noise and offset, without penalizing delay nor power consumption. In fact, the proposed topology is even more efficient than its conventional counterpart as it exhibits lower power consumption when the two circuits are sized to have the same delay. The operation of the new topology is analyzed in detail through a comprehensive theoretical analysis, providing useful design criteria. The enhanced Strong Arm comparator is validated by means of post-layout simulations in a 55 nm CMOS technology with 1 V supply. The simulations show that the proposed approach improves noise, offset and energy-delay product (EDP) respectively by 28.5%, 33.8% and 5.24% compared to the conventional Strong Arm latch.

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