The in-situ doping of aluminum and nitrogen in migration enhanced embedded epitaxy (ME3) is investigated with the aim to apply it to the realization and fabrication of all-epitaxial, normally-off 4H-SiC JFET devices. This ME3 process consists of the epitaxial growth of an n-doped channel and a highly p-doped top gate in narrow trenches. We found that the nitrogen doping in the n-channel (a-face) is a factor 1.5 higher than layers grown with the same process on Si-face wafers. Due to the low C/Si ratio and the low silane flow rate used in the ME3 process, the growth of the p-doped top gate needs high flow rates of the aluminum precursor trimethylaluminum for several hours, which contaminates the CVD reactor and causes aluminum memory effects. These aluminum memory effects can be reduced by an extra high temperature bake-out run.

This paper reviews the normally‐off (N‐ off) and normally‐on (N‐ on) SiC junction field effect transistor (JFET) concepts and presents an innovative all‐epitaxial double‐gate trench JFET (DGTJFET) structure. The DGTJFET design combines the advantages of lateral and buried gate JFET concepts. The lateral JFET advantage is the epitaxial definition of the channel width and the buried gate JFET advantage is the small cell size. In the DGTJFET process the epitaxial embedded growth in trenches facilitates the small cell pitch and the vertical direction of the channel. A detailed numerical simulation analysis compares the potential of the DGTJFET design with reported lateral channel and buried gate JFET structures. Migration enhanced embedded epitaxy (ME3) and planarization processes were developed to realize narrow cell pitch DGTJFETs for high‐density power integration. The highly doped vertical channel of the DGTJFET defined by the ME3 growth process makes it possible to accurately control the sub‐micron channel dimensions in order to realize a low specific on‐state resistance (RON) and a high saturation current capability. The anisotropic nature of SiC is taken into account for the channel design considerations. The successful application of the new process technologies for the development of the all‐epitaxial DGTJFETs is discussed. Fabricated 5.5 μm cell pitch 4H‐SiC DGTJFETs demonstrate the saturation current density capability of more than 1000 A/cm2. N‐ off and N‐ on DGTJFETs with 2.25 mm squared chip size and 9.5 μm cell pitch output 15 A and 20 A at gate voltage of 2.5 V and drain voltage of 5.0 V. The specific RON of the N‐ off and N‐ on DGTJFETs is at room temperature 8.1 m Ω cm2 and 6.3 mΩ cm2, respectively, indicating that N‐ off devices can be realized at the expense of a slight increase in specific RON of approximately 25%. DGTJFETs with a 13 μm drift layer doped to 5.0 × 1015 cm–3 are demonstrated with a breakdown voltage in the range of 1200 V to 1550 V at the wafer level with a leakage current below 10 μA. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

In this work, we have developed an innovative epitaxial growth process named the “Migration Enhanced Embedded Epitaxial” (ME3) growth process. It was found that at elevated growth temperatures, the epitaxial growth at the bottom of the trenches is greatly enhanced compared to growth on the sidewalls. This is attributed to the large surface diffusion length of reactant species mainly due to the higher growth temperature. In addition, it was found that this high temperature ME3 growth process is not influenced by the crystal-orientation. Similar growth behavior was observed for stripe-trench structures aligned either along the [11-20] or [1-100] directions. No difference was observed in the electrical performance of the pn diodes fabricated on either oriented stripe geometry. The ME3 process can also be used as an alternative to ion-implantation technology for selective doping process.

The migration enhanced embedded epitaxy (ME3) mechanism and 2D dopant distribution of the embedded trench region is investigated with the aim to realize the all-epitaxial, normally-off junction field effect transistor (JFET). We found that the embedded growth consists of two main components. First one is the direct supply without gas scattering and the other one is the surface migration supply via the trench opening edge, which dominate the ME3 process. An inhomogeneous 2D distribution of Aluminum (Al) concentration was revealed for the first time in the 4H-SiC embedded trench regions by the combined analysis of secondary ion mass spectrometry (SIMS) and scanning spreading resistance microscopy (SSRM) results. The maximum variation of Al concentration in the trench is estimated to be about 4-times, which suggests that the Al concentration is highest for the (0001) plane and lowest for the trench corner (1-10x) plane. Al concentration in the (1-100) plane, which determines the JFET p-gate doping level is 1.5-times lower than (0001) plane for trench region fabricated on Si-face wafers.

In this work, we have developed a selective embedded epitaxial growth process on 150-mm-diameter wafer by vertical type hot wall CVD reactor with the aim to realize the all-epitaxial 4H-SiC MOSFETs [1, 2, 3, 4, 5]. We found that at elevated temperature and adding HCl, the epitaxial growth rate at the bottom of trench is greatly enhanced compare to growth on the mesa top. And we obtain high growth rate 7.6μm/h at trench bottom on 150mm-diameter-wafer uniformly with high speed rotation (1000rpm).

An investigation concerning suitable termination techniques for 4H-SiC trench JFETs is presented. Field plates, p+ floating rings and junction termination extension techniques are used to terminate 1.2kV class PiN diodes. The fabricated PiN diodes evaluated here have a similar design to trench JFETs. Therefore, the conclusions for PiN diodes can be applied to JFET structures as well. Numerical simulations are also used to illustrate the effect of the terminations on the diodes’ blocking mode behaviour.

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Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6 – 10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5 – 1.8kV was realized at VGS = −5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design.