Evaluation of Termination Techniques for 4H-SiC Pin Diodes and Trench JFETs

Mihaila, A.; Udrea, F.; Rashid, S.J.; Amaratunga, G.A.J.; Kataoka, Mitsuhiro; Takeuchi, Yuuichi; Malhan, Rajesh Kumar

doi:10.4028/www.scientific.net/msf.556-557.925

Cited by 6 publications

(3 citation statements)

References 5 publications

(5 reference statements)

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“…The recessed area angle is considered in the termination design. With the narrow multiple FGRs design higher blocking capabilities can be realized, but the process window is comparatively narrower than the JTE design [32]. need to consider various anisotropic aspects of the inherent material properties.…”

Section: Off-state Characteristicsmentioning

confidence: 99%

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

Malhan

Bakowski

Takeuchi

et al. 2009

Physica Status Solidi (a)

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This paper reviews the normally‐off (N‐ off) and normally‐on (N‐ on) SiC junction field effect transistor (JFET) concepts and presents an innovative all‐epitaxial double‐gate trench JFET (DGTJFET) structure. The DGTJFET design combines the advantages of lateral and buried gate JFET concepts. The lateral JFET advantage is the epitaxial definition of the channel width and the buried gate JFET advantage is the small cell size. In the DGTJFET process the epitaxial embedded growth in trenches facilitates the small cell pitch and the vertical direction of the channel. A detailed numerical simulation analysis compares the potential of the DGTJFET design with reported lateral channel and buried gate JFET structures. Migration enhanced embedded epitaxy (ME3) and planarization processes were developed to realize narrow cell pitch DGTJFETs for high‐density power integration. The highly doped vertical channel of the DGTJFET defined by the ME3 growth process makes it possible to accurately control the sub‐micron channel dimensions in order to realize a low specific on‐state resistance (RON) and a high saturation current capability. The anisotropic nature of SiC is taken into account for the channel design considerations. The successful application of the new process technologies for the development of the all‐epitaxial DGTJFETs is discussed. Fabricated 5.5 μm cell pitch 4H‐SiC DGTJFETs demonstrate the saturation current density capability of more than 1000 A/cm2. N‐ off and N‐ on DGTJFETs with 2.25 mm squared chip size and 9.5 μm cell pitch output 15 A and 20 A at gate voltage of 2.5 V and drain voltage of 5.0 V. The specific RON of the N‐ off and N‐ on DGTJFETs is at room temperature 8.1 m Ω cm2 and 6.3 mΩ cm2, respectively, indicating that N‐ off devices can be realized at the expense of a slight increase in specific RON of approximately 25%. DGTJFETs with a 13 μm drift layer doped to 5.0 × 1015 cm–3 are demonstrated with a breakdown voltage in the range of 1200 V to 1550 V at the wafer level with a leakage current below 10 μA. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

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Section: Off-state Characteristicsmentioning

confidence: 99%

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

Malhan

Bakowski

Takeuchi

et al. 2009

Physica Status Solidi (a)

Self Cite

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“…Trench JFET fabrication process details are given elsewhere [1]. Floating guard ring (FGR) design was used for the cell edge termination [4].…”

Section: Methodsmentioning

confidence: 99%

Switching Performance of Epitaxially Grown Normally-Off 4H-SiC JFET

Malhan

Rashid

Kataoka

et al. 2008

MSF

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Static and dynamic behavior of the epitaxially grown dual gate trench 4H-SiC junction field effect transistor (JFET) is investigated. Typical on-state resistance Ron was 6 – 10mΩcm2 at VGS = 2.5V and the breakdown voltage between the range of 1.5 – 1.8kV was realized at VGS = −5V for normally-off like JFETs. It was found that the turn-on energy delivers the biggest part of the switching losses. The dependence of switching losses from gate resistor is nearly linear, suggesting that changing the gate resistor, a way similar to Si-IGBT technology, can easily control di/dt and dv/dt. Turn-on losses at 200°C are lower compared to those at 25°C, which indicates the influence of the high internal p-type gate layer resistance. Inductive switching numerical analysis suggested the strong influence of channel doping conditions on the turn-on switching performance. The fast switching normally-off JFET devices require heavily doped narrow JFET channel design.

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“…However the protection efficiency of FGR is not enough for the ultrahigh voltage SiC power devices [2,3]. Junction termination extension (JTE) was widely used because of high termination efficiency, however the protection efficiency of JTE is limited by interface charge [4,5]. To eliminate the negative influence of interface charge to the protection efficiency, multiple implantations must be done [6,7,8].…”

Section: Introductionmentioning

confidence: 99%

Development of g10kv 4H-SiC SBD junction extension termination

Huang¹,

Tao²,

Chen³

et al. 2016

Proceedings of the 2016 International Conference on Advanced Electronic Science and Technology (AEST 2016)

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10kV 4H-SiC JBS diodes with various junction extension terminations have been experimentally realized. The protection efficiencies of single JTE and modulation JTE terminations were investigated by means of numerical simulations. The JTE dose window to achieve the high protection efficiency has been enlarged, which indicates the robustness to the deviation of effective JTE dose and SiO2/SiC interface charge. The samples with the single JTE, two-zone JTE, three-zone JTE and improved three-zone JTE terminations were fabricated. With the modulation JTE, the typical breakdown voltage of 13.5 kV corresponding to protection efficiency of 95% has been achieved, and the various JTE terminations were compared and discussed.

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Evaluation of Termination Techniques for 4H-SiC Pin Diodes and Trench JFETs

Cited by 6 publications

References 5 publications

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

Design, process, and performance of all‐epitaxial normally‐off SiC JFETs

Switching Performance of Epitaxially Grown Normally-Off 4H-SiC JFET

Development of g10kv 4H-SiC SBD junction extension termination

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