No abstract

In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52

No abstract

Complex QR factorisation is a fundamental operation used in various applications such as adaptive beamforming and MIMO signal detection. In this paper, based on Givens rotation scheme, a high-throughput, fully parallel complex-valued QR factorisation (CQRF) design is presented. It features the lowest computing complexity in various factorising schemes and indicates no BER performance loss when applied to a MIMO signal detection system. Via carefully plotted scheduling, one CQRF computation can be completed in eight clock cycles. In hardware design, a low complexity and look-up-table-free CORDIC algorithm is employed to implement the rotation operations. Further design optimisations, such as hardware sharing of common modules and reduction of register usage by shortening the variable's life span, are also applied. Sized 22 and 44 chip designs largely following the IEEE 802.11n standard are developed. The implementation results in TSMC 0.18 um process technology show that the proposed 44 design, with a gate count of only 134.6 K, is capable of performing 15 M CQRFs per second. The measured power consumption is 196.3 mW at 120 MHz. Compound performance indexes such as area-time product and energy consumption per CQRF also indicate significant performance edges of the proposed designs

In this letter, an efficient lossless compression scheme for hyperspectral images is presented. The proposed scheme uses a two-stage predictor. The stage-1 predictor takes advantage of spatial data correlation and formulates the derivation of a spectral domain predictor as a process of Wiener filtering. The stage-2 predictor takes the prediction from the stage-1 predictor as an initial value and conducts a backward pixel search (BPS) scheme on the current band for the final prediction value. Experimental results show that the BPS scheme, aimed at exploiting calibration-induced data correlation, is effective on Airborne Visible/Infrared Imaging Spectrometer (AVIRIS) 1997 images where such artifacts are significant. The proposed work outperforms all other schemes under comparison in this category. For the newer Consultative Committee for Space Data Systems images where calibration-induced artifacts are minimized, the BPS scheme does not help, and the stage-1 predictor alone achieves better compression performance

No abstract

A novel low-power sense-amplifier-based flip-flop (FF) is presented. Using a simplified single-ended pass transistor-based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense-amplifier design as well. These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive postlayout simulations.Introduction: Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules. FFs thus contribute a significant portion of chip area and power consumption to the overall system design [1]. Numerous FF designs have been presented to meet various application demands [2-6]. Among them is the sense-amplifier-based FF design [2], which consists of a dynamic logic sense amplifier followed by an SR latch, and is shown in Fig. 1a. It exhibits smaller setup time and better power performance than conventional TGFF, and is thus considered a better design candidate to achieve both speed and power goals. Two practical problems, however, exist in this FF design. First, the effectiveness of switching power reduction diminishes at lower or zero data switching and the power consumption of the precharge operations by the sense amplifier dominates. Secondly, the NAND-based SR latch admitting the data setting signals from the sense amplifier causes a longer clock to Q (C-to-Q) delay [4][5][6]. It is also observed that, in many applications, complementary FF outputs are not necessary.

No abstract