A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

Carbon nanotube field-effect transistors (CNFETs) utilize an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure, which holds great promise for the future of integrated circuits. In this paper, a full adder cell based on a parallel design using CNFETs is presented. The main objective of designing this full adder cell is to reduce critical path delay in CNFET-based adder circuits. The proposed design positively affects speed and power consumption by shortening the data path. In order to evaluate the proposed design, several simulations were performed with different load capacitors, frequencies, and temperatures using HSPICE in 32-nm CMOS and 32-nm CNFET technologies. The proposed full adder cells were compared with five other full adder cells using 4-bit ripple carry adder (RCA) and 8-bit RCA circuits with power consumption, speed, and power delay product parameters. The obtained results indicate that the proposed design is faster than other designs due to a shortened data path. The results of the simulations confirm the higher efficiency of the proposed full adder cell with respect to other designs.

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“…The last full adder cell that is discussed here is CLRCLFA, presented in [12]. The circuit of this full adder cell is shown in Figure 6.…”

Section: Previous Workmentioning

confidence: 99%

A CNFET full adder cell design for high-speed arithmetic units

Ghanatghestani¹,

Ghavami²,

Salehpour³

2017

Turk J Elec Eng & Comp Sci

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“…MB12T [15] has been implemented using six multiplexers and 12 transistors. Each multiplexer is implemented by pass-transistor logic with two transistors.…”

Section: T Full Adder Circuitmentioning

confidence: 99%

Comparative Analysis of Different Types of Full Adder Circuits

Damle¹

2013

IOSR-JCE

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“…Boolean functions for this architecture are given by equations (7)- (10). In this architecture G is computed as the generate function of a CLA, while we use the inverted kill function, denoted by H, instead of the more commonly used propagate function P. …”

Section: Radix-2 Fa With Pre-computed G/h Signalsmentioning

confidence: 99%

Performance analysis of radix-4 adders

Asif

Vesterbacka

2012

Integration

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Abstract-We present a radix-4 static CMOS full adder circuit that reduces the propagation delay, PDP, and EDP in carrybased adders compared with using a standard radix-2 full adder solution. The improvements are obtained by employing carry look-ahead technique at the transistor level. Spice simulations using 45 nm CMOS technology parameters with a power supply voltage of 1.1 V indicate that the radix-4 circuit is 24% faster than a 2-bit radix-2 ripple carry adder with slightly larger transistor count, whereas the power consumption is almost the same. A second scheme for radix-2 and radix-4 adders that have a reduced number of transistors in the carry path is also investigated. Simulation results also confirm that the radix-4 adder gives better performance as compared to a standard 2-bit CLA. 32-bit ripple carry, 2-stage carry select, variable size carry select, and carry skip adders are implemented with the different full adders as building blocks. There are PDP savings, with one exception, for the 32-bit adders in the range 8% to 18% and EDP savings in the range 21% to 53% using radix-4 as compared to radix-2.

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A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

Cited by 170 publications

References 6 publications

A CNFET full adder cell design for high-speed arithmetic units

A CNFET full adder cell design for high-speed arithmetic units

Comparative Analysis of Different Types of Full Adder Circuits

Performance analysis of radix-4 adders

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