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In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52

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This paper presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image. 3) lower data access times from the image memory, 4) shorter latency, 5) suitability for VLSI implementation, and 6 ) adaptability for N*N morphologic operations.

In this paper we propose a flexible 4-moduli set (2 p+k , 2 p +1, 2 p -1, 2 2p +1) which is profitable to construct a high-speed residue number system (RNS). We derive a simple reverse conversion algorithm for the proposed moduli set by using Chinese Remainder Theorem (CRT). The resulting converter architecture mainly consists of simple adders which are suitable to realize an efficient VLSI implementation. Based on TSMC 0.13um CMOS technology, the proposed reverse converter demonstrates its superiority in terms of area, delay and power over the converter design for the 4-moduli set (2 n , 2 n -1, 2 n +1, 2 2n +1) under the various dynamic range (DR) requirements. Finally, the chip area, the clock rate and the power consumption of the proposed 32-bit reverse RNS converter are 1227x1227um 2 , 105MHz and 1.3mW respectively.