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In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an AND function, is removed from the critical path to facilitate a faster discharge operation. A simple two-transistor AND gate design is used to reduce the circuit complexity. Second, a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed. As a result, transistor sizes in delay inverter and pulse-generation circuit can be reduced for power saving. Various postlayout simulation results based on UMC CMOS 90-nm technology reveal that the proposed design features the best power-delay-product performance in seven FF designs under comparison. Its maximum power saving against rival designs is up to 38.4%. Compared with the conventional transmission gate-based FF design, the average leakage power consumption is also reduced by a factor of 3.52

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This study aims to investigate the estrus efficacy of FIS (fluorogestone intravaginal sponges)/eCG (equine chorionic gonadotropin) and cloprostenol treatments to establish the optimum protocols for estrus synchronization in ewes. Forty-two ewes were assigned into groups A (FIS/eCG group) and B (CLO (cloprostenol) group). Each group was randomly divided into three subgroups (n = 7) according to the dose of eCG (ECG1, ECG2 and ECG3) or cloprostenol (CLO1, CLO2 and CLO3). The estrus rates, lambing rates and average litter sizes were accounted. Serum concentrations of progesterone (P4), folliclestimulating hormone (FSH) and luteinizing hormone were determined. Selected optimum schemes were employed in 636 ewes in four sheep farms. Estrus rates of groups A and B were 85.72% and 57.14%. Estrus onset times (EOTs) were 53.91 ± 12.26 and 46.41 ± 4.65 h for groups A and B. EOT of ECG1 was longer than that of CLO3 (P < .05). Lamb numbers, lambing rate and litter size of group B were lower than those of group A. The maximum and minimum lambing rates were calculated in ECG3 and CLO1 (157 vs. 57). On day 11, higher P4 values (P < .05) were determined of ECG3 and CLO1 compared to CLO2 and CLO3 subgroups. FSH concentration of ECG1 was significantly higher than that in group B (P < .05). Application results showed that estrus rate, pregnancy rate and lambing rates of ECG3 and CLO3 protocols were 95.97% vs. 70.91%, 91.37% vs. 88.89% and 149.87% vs 132.69% (P < .05), respectively. FIS/eCG and cloprostenol improved estrus synchronization. Injection of 400 IU eCG after FIS withdrawal was an optimum protocol for estrus synchronization of ewes. ARTICLE HISTORY

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A novel low-power sense-amplifier-based flip-flop (FF) is presented. Using a simplified single-ended pass transistor-based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense-amplifier design as well. These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive postlayout simulations.Introduction: Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules. FFs thus contribute a significant portion of chip area and power consumption to the overall system design [1]. Numerous FF designs have been presented to meet various application demands [2-6]. Among them is the sense-amplifier-based FF design [2], which consists of a dynamic logic sense amplifier followed by an SR latch, and is shown in Fig. 1a. It exhibits smaller setup time and better power performance than conventional TGFF, and is thus considered a better design candidate to achieve both speed and power goals. Two practical problems, however, exist in this FF design. First, the effectiveness of switching power reduction diminishes at lower or zero data switching and the power consumption of the precharge operations by the sense amplifier dominates. Secondly, the NAND-based SR latch admitting the data setting signals from the sense amplifier causes a longer clock to Q (C-to-Q) delay [4][5][6]. It is also observed that, in many applications, complementary FF outputs are not necessary.

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