Single‐ended structure sense‐amplifier‐based flip‐flop for low‐power systems

Abstract

A novel low-power sense-amplifier-based flip-flop (FF) is presented. Using a simplified single-ended pass transistor-based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense-amplifier design as well. These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive postlayout simulations.Introduction: Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules. FFs thus contribute a significant portion of chip area and power consumption to the overall system design [1]. Numerous FF designs have been presented to meet various application demands [2-6]. Among them is the sense-amplifier-based FF design [2], which consists of a dynamic logic sense amplifier followed by an SR latch, and is shown in Fig. 1a. It exhibits smaller setup time and better power performance than conventional TGFF, and is thus considered a better design candidate to achieve both speed and power goals. Two practical problems, however, exist in this FF design. First, the effectiveness of switching power reduction diminishes at lower or zero data switching and the power consumption of the precharge operations by the sense amplifier dominates. Secondly, the NAND-based SR latch admitting the data setting signals from the sense amplifier causes a longer clock to Q (C-to-Q) delay [4][5][6]. It is also observed that, in many applications, complementary FF outputs are not necessary.

A Low-Power High-Speed Sense-Amplifier-Based Flip-Flop in 55 nm MTCMOS

“…In [10], Kim et al proposed a SAFF with a latch composed of two N-C 2 MOS circuits and two pairs of inverters as shown in Figure 3a. Lin et al improved the latch in [10] to a single-ended structure, which reduced the power consumption substantially [11]. The schematic of the latch in Lin's SAFF is shown in Figure 3b.…”

A Novel Low Power, Minimal Dead Zone Digital PFD for Biomedical Applications

“…4: Sense amplifier block is the name given because it is sensed with a clock signal and additional differential inputs and produces complemented inputs to the slave latch. Slave latch is designed as an SR (Set-Reset) latch that has been ignited by either SB or RB (but not both) created by the master block [11][12][13][14][15][16]. The entire design of SAFF portrays the flip flop process as the Sense amplifier block produces uniform transitions from logic zero to logic one on any output based on the leading edge of the clock distribution.…”

“…The output state generated can now be processed and the slave latch can be held until the next leading edge of the clock signal arrives. Once the clock is inactive, both outputs of the master block assume high logic [11][12][13][14][15][16].…”

“…The smallest path for RB is through NM2, NM4 and NM5 when DB is logic H by turning NM1 OFF and PM1 ON. Further alterations of input data should not affect the status of SB and RB after these initial changes [11][12][13][14][15][16]. The complete operation of sense amplifier can be described in Table I.…”

“…In the technical market there are various types of latches to select the right one. The best latches for power consumption circuits include the latches such as Nikolic's [11][12][13], Kim's [17], Strollo's [18]. Comparative parameters such as rise delay, fall delay, power consumption and power delay product (PDP) descriptions of these latches are shown in Table II.…”