In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.
This paper presents a novel 12T SRAM bitcell suitable for subthreshold operation. To make bit-interleaving structure feasible and eliminate half-select disturbance, the proposed cell features single pass-gate and dual pass-gates for read and write operation respectively. Additionally, the access path is decoupled by dedicate transistors from the true storage node, which both enhances the read stability and ensures enough sensing margin. Multi-threshold voltage metric is utilized to improve writability and leakage consumption. Simulation results show that the proposed cell offers 1.8X read static noise margin (RSNM) and 1.6X negative write static noise margin (WSNM) compared with traditional 6T cell at 0.4 V, sensing margin and access performance are improved compared with 10T cell.
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