In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed operation is proposed. With the employment of a new sense-amplifier stage as well as a new single-ended latch stage, the power and delay of the flip-flop is greatly reduced. A conditional cut-off strategy is applied to the latch to achieve glitch-free and contention-free operation. Furthermore, the proposed SAFF can provide low voltage operation by adopting MTCMOS optimization. Post-layout simulation results based on a SMIC 55 nm MTCMOS show that the proposed SAFF achieves a 41.3% reduction in the CK-to-Q delay and a 36.99% reduction in power (25% input data toggle rate) compared with the conventional SAFF. Additionally, the delay and the power are smaller than those of the master-slave flip-flop (MSFF). The power-delay-product of the proposed SAFF shows 2.7× and 3.55× improvements compared with the conventional SAFF and MSFF, respectively. The area of the proposed flip-flop is 8.12 μm2 (5.8 μm × 1.4 μm), similar to that of the conventional SAFF. With the employment of MTCMOS optimization, the proposed SAFF could provide robust operation even at supply voltages as low as 0.4 V.
Whether stroke-induced paretic muscle changes vary across different distal and proximal muscles remains unclear. The objective of this study was to compare paretic muscle changes between a relatively proximal muscle (the biceps brachii muscle) and two distal muscles (the first dorsal interosseous muscle and the abductor pollicis brevis muscle) following hemisphere stroke using clustering index (CI) analysis of surface electromyograms (EMGs). For each muscle, surface EMG signals were recorded from the paretic and contralateral sides of 12 stroke subjects versus the dominant side of eight control subjects during isometric muscle contractions to measure the consequence of graded levels of contraction (from a mild level to the maximal voluntary contraction). Across all examined muscles, it was found that partial paretic muscles had abnormally higher or lower CI values than those of the healthy control muscles, which exhibited a significantly larger variance in the CI via a series of homogeneity of variance tests (p < 0.05). This finding indicated that both neurogenic and myopathic changes were likely to take place in paretic muscles. When examining two distal muscles of individual stroke subjects, relatively consistent CI abnormalities (toward neuropathy or myopathy) were observed. By contrast, consistency in CI abnormalities were not found when comparing proximal and distal muscles, indicating differences in motor unit alternation between the proximal and distal muscles on the paretic sides of stroke survivors. Furthermore, CI abnormalities were also observed for all three muscles on the contralateral side. Our findings help elucidate the pathological mechanisms underlying stroke sequels, which might prove useful in developing improved stroke rehabilitation protocols.
Background: There is a great demand for convenient and quantitative assessment of upper-limb traumatic peripheral nerve injuries (PNIs) beyond their clinical routine. This would contribute to improved PNI management and rehabilitation. Objective: The aim of this study was to develop a novel surface EMG examination method for quantitatively evaluating traumatic upper-limb PNIs. Methods: Experiments were conducted to collect surface EMG data from forearm muscles on both sides of seven male subjects during their performance of eight designated hand and wrist motion tasks. All participants were clinically diagnosed as unilateral traumatic upper-limb PNIs on the ulnar nerve, median nerve, or radial nerve. Ten healthy control participants were also enrolled in the study. A novel framework consisting of two modules was also proposed for data analysis. One module was first used to identify whether a PNI occurs on a tested forearm using a machine learning algorithm by extracting and classifying features from surface EMG data. The second module was then used to quantitatively evaluate the degree of injury on three individual nerves on the examined arm. Results: The evaluation scores yielded by the proposed method were highly consistent with the clinical assessment decisions for three nerves of all 34 examined arms (7 × 2 + 10 × 2), with a sensitivity of 81.82%, specificity of 98.90%, and significate linear correlation (p < 0.05) in quantitative decision points between the proposed method and the routine clinical approach. Conclusion: This study offers a useful tool for PNI assessment and helps to promote extensive clinical applications of surface EMG.
An ultra-low leakage energy efficient level shifter that can convert extremely low input voltage into the supply voltage level is presented in this paper. In order to reduce the leakage power dissipation, the super-cutoff mechanism and MTCMOS technique are utilized in the proposed structure. At the same time, a positive feedback circuit is inserted to avoid the loss of performance. Post-layout simulation results in a 55-nm MTCMOS process demonstrate that for the voltage level conversion from 0.3 V to 1.2 V, the proposed level shifter exhibits a propagation delay of 70.77 ns and an energy per transition of 89.55 fJ for input frequency of 1 MHz. Meanwhile, the static power of the proposed level shifter is as low as 27.82 pW. The proposed level shifter only occupies 7.79 um 2 , which demonstrates prominent area efficiency.
In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed CSLAs reduced power consumption by 68.4–72.2% with a slight delay increase for different bit widths. As the dual carry adder had much fewer transistors than the two regular full adders, the area of the proposed CSLAs was reduced by 45.8–51.1%. The area-power-delay product of the proposed CSLA improved 5.1×–6.73× compared with the regular CSLA.
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