An ultra-low leakage energy efficient level shifter with wide conversion range

You, Heng; Jia, Yuping; Tang, Weidi; Yu, Yi; Qiao, Shushan; Hei, Yong

doi:10.1587/elex.16.20190507

Cited by 5 publications

(2 citation statements)

References 32 publications

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“…However, this approach is accompanied by significant power consumption when dealing with highvoltage input signals, hence making it less suitable for low-power devices. The authors in reference [16] present an LS that effectively converts a lower input voltage to high output voltage. This architecture design incorporates the MTCMOS method and the super-cut-off mechanism in order to mitigate power dissipation resulting from leakage.…”

Section: Introduction and Literature Surveymentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

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Section: Introduction and Literature Surveymentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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“…Therefore, ultra-low-power systems should not use this architecture. In [8], In this article, the development of a level shifter circuit that is capable of efficiently transforming a lower input voltage to the desired voltage level while minimizing the amount of leakage current has proposed. The super-cut-off mechanism and MTCMOS method are included into the suggested structure to reduce power leakage as much as possible.…”

Section: Introductionmentioning

confidence: 99%

Development of compact voltage level-up shifter for nano-second delay system-on-chip applications

Sudhakar,

Gutta

2023

Eng. Res. Express

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The Level Shifter is made with two inverters and a Wilson current mirror to use less energy. In order to reduce the amount of leaking power, this study suggests using a combination of super-cut-off draw-down and stacked pull-up networks. The design also incorporates MTCMOS technology, which, consists of sleeper transistors that are able to boosts performance without increasing either power usage or size. The designed device can be used to shift voltage in between 0.4 V and 1.2 V. To suit nano-scale uses, the circuit's operating range and performance factors (such as power, latency, and area) were fine-tuned. According to the results, "level-up" transitions typically consume 148.6nW of active power and have an average delay of 1.19 ns at 1 MHz transmission rates. The post-layout model indicated that the recommended plan would need 9.47 µm2 of floor space. The results are analyzed in Cadence Virtuoso using 45nm techniques.

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An ultra-low leakage and small-area level shifter based on super-cut-off mechanism

Wang

You

et al. 2022

AEU - International Journal of Electronics and Communications

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An ultra-low leakage energy efficient level shifter with wide conversion range

Cited by 5 publications

References 32 publications

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Development of compact voltage level-up shifter for nano-second delay system-on-chip applications

An ultra-low leakage and small-area level shifter based on super-cut-off mechanism

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