An ultra-low leakage and small-area level shifter based on super-cut-off mechanism

Wang, Peng; Wang, Xiaoqin; You, Heng; Yin, Jialu; Zhan, Yiqiang; Qiao, Shushan; Zhou, Yumei

doi:10.1016/j.aeue.2021.154085

Cited by 2 publications

(2 citation statements)

References 31 publications

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“…The circuit demonstrated notable improvements in power and efficiency by employing a reduction in the number of transistors to 5, while also achieving a decrease in transmission delay to 4.95 ns. Wang et al developed a LS [6] that was meant to have minimal space requirements and low leakage current. This approach employs a multi-layer pull-up and pull-down system to mitigate energy dissipation.…”

Section: Introduction and Literature Surveymentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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The objective of this study is to present a level shifter architecture that utilizes a pair of inverters and a Wilson current mirror to reduce power consumption while improving voltage shifting capabilities. We introduce novel components such as super-cut-off pull-down and stacked pull-up networks to effectively minimize leakage power. Our design leverages multi-threshold CMOS (MTCMOS) technology, incorporating sleep transistors to boost operational speed, decrease power consumption, and reduce the physical footprint. The proposed circuit is engineered to step up voltage levels, ranging from a mere 0.4 V to a substantial 1.2 V. Through extensive optimization of performance parameters, including power efficiency, delay, and area utilization, we have tailored this design to cater specifically to the demands of nano-scale applications. Key results from our research reveal that the average active power consumption for “level-up” shifts is impressively low at 48.5 nW, with an average latency of a mere 1.58 ns for 1 MHz transmission frequencies. Post-layout modeling demonstrates that our suggested design occupies a compact area of just 9.97 µm2. These findings were meticulously modeled using Cadence Virtuoso with 45 nm processes. Furthermore, our research highlights the substantial advancements achieved when compared to previous methods. The proposed design boasts a threefold increase in operational speed and delivers significant savings in both area and power consumption. These outcomes have far-reaching implications for emerging technologies and applications in the field.

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Section: Introduction and Literature Surveymentioning

confidence: 99%

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Sudhakar,

Stan

2023

Electronics

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“…The CMOS technology used here permits a voltage range of 3 to 8.5 V, with a tolerance of 1.8 to 3.3 V. Latency is around 1.8 ns, and the footprint is 0.008 mm 2 . In [3], the level shifter in the system has ultra-low leakage power-consumption and space efficient. The input-side inverter, current mirror circuit of Wilson-type, and output-generating inverter operate together with a super-cut-off pull-down and stackable pull-up network to reduce power leakage.…”

Section: Introductionmentioning

confidence: 99%

Development of compact voltage level-up shifter for nano-second delay system-on-chip applications

Sudhakar,

Gutta

2023

Eng. Res. Express

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The Level Shifter is made with two inverters and a Wilson current mirror to use less energy. In order to reduce the amount of leaking power, this study suggests using a combination of super-cut-off draw-down and stacked pull-up networks. The design also incorporates MTCMOS technology, which, consists of sleeper transistors that are able to boosts performance without increasing either power usage or size. The designed device can be used to shift voltage in between 0.4 V and 1.2 V. To suit nano-scale uses, the circuit's operating range and performance factors (such as power, latency, and area) were fine-tuned. According to the results, "level-up" transitions typically consume 148.6nW of active power and have an average delay of 1.19 ns at 1 MHz transmission rates. The post-layout model indicated that the recommended plan would need 9.47 µm2 of floor space. The results are analyzed in Cadence Virtuoso using 45nm techniques.

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An ultra-low leakage and small-area level shifter based on super-cut-off mechanism

Cited by 2 publications

References 31 publications

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Implementation of High-Speed Compact Level-Up Shifter for Nano-Scale Applications

Development of compact voltage level-up shifter for nano-second delay system-on-chip applications

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