Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

Hwang, Yin-Tsung; Lin, Jin-Fa; Sheu, Ming‐Hwa

doi:10.1109/tvlsi.2010.2096483

Cited by 66 publications

(51 citation statements)

References 14 publications

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“…Since pulse width design is crucial to the correctness of data capture as well as the power consumption [10]- [13], the transistors of the pulse generator logic are sized for a design spec of 120 ps in pulse width in the TT case. The sizing also ensures that the pulse generators can function properly in all process corners.…”

Section: Simulation Resultsmentioning

confidence: 99%

Design of Low Power 8-Bit Shift Register using PFF

2017

International Journal of Emerging Engineering Research and Tech

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In this brief, Design of low-power 8-bit shift register is done by using flip-flop (FF) design featuring an explicit type pulse-triggered structure based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Using 8-bits of PFF 8-Bit shift register is designed. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power delay product metrics are 22.7% and 29.7%, respectively. The objective of the project is to design 8-bit shift register using pulse triggered flip flop with signal feed through scheme which consumes less power and delay will be reduced. In this project different implicit and explicit type flip flops are simulated in Hspice using 180nm technology whereas proposed design circuit is simulated in Hspice using 90nm technology.

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Section: Simulation Resultsmentioning

confidence: 99%

Design of Low Power 8-Bit Shift Register using PFF

2017

International Journal of Emerging Engineering Research and Tech

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“…1 (ip-DCO [4]), Fig. 2 (CPE-PTFF [5]). The proposed flip-flop is implemented in 90nm CMOS technology at room temperature using HiSIM level 68 model HSPICE.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Fig . 2 shows a conditional pulse enhancement based PTFF (CPE-PTFF) [5], which adopts two measures to overcome the difficulties encountered with the existing PTFF designs. The…”

Section: Proposed Low Power Pulsed Flip-flop 21 Conventional Pulse Tmentioning

confidence: 99%

Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic

Rao¹,

Rajendar²

2013

IJCA

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In this paper, a low power implicit type pulsed flip-flop (PFF) using self-driven pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. The pass transistor logic driven by generated clock pulse is used directly to drive the output of the flip-flop. The proposed design is compared with the conventional implicit type data close to output (ip-DCO) flipflop. As compared to the conventional pulse triggered flipflop, the proposed pulsed flip-flop (PFF) design features best speed, power and power-delay-product performance. The proposed technique is implemented using HSPICE CMOS 90nm technology. The average power consumption for 50% switching activity is reduced by 12.75% as compared to conventional ip-DCO.

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“…In order to reduce that dual edge triggered flip flop is discussed. Here conditional capture, conditional precharge, conditional discharge, and conditional pulse enhancement scheme techniques [2] are discussed. They suffer from longer discharging path hence the data transition takes more time.…”

Section: Related Workmentioning

confidence: 99%

“…Some techniques are used to overcome this problem. They are conditional capture, conditional precharge, conditional discharge, and conditional pulse enhancement scheme [2]. shows the static conditional discharge technique.…”

Section: Existing Designsmentioning

confidence: 99%

Design of Low Power Dual Edge Triggered Flip Flop Based On Signal Feed through Scheme

THA¹,

ESH²

2014

IJAREEIE

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A low power dual edge triggered flip flop based on a signal feed through scheme is presented. The power consumption is the major problem in circuit design. The proposed deign reduces power and delay compared to explicit pulse triggered flip flop. Reducing the number of transistor in the stack and increasing the number of charge path leads to higher operational speed compared to others flip-flops. Double-edge-triggered flip flops (DETFFs) are recognized as power-saving flip flops. The dual edge triggered design operates in a low voltage range and hence it is suited for low voltage application. This flip flop uses weak feedback transistor but without static power consumption. This reduces leakage current and thus saves the power. By using low clock frequency high throughput can be achieved. The simulation is done using Tanner EDA Tool v14 with CMOS 90nm technology.

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Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

Cited by 66 publications

References 14 publications

Design of Low Power 8-Bit Shift Register using PFF

Design of Low Power 8-Bit Shift Register using PFF

Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic

Design of Low Power Dual Edge Triggered Flip Flop Based On Signal Feed through Scheme

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