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In this paper, a novel low power 20T alternative adder cell featuring modified swing restored complementary pass transistor logic (SR-CPL) is proposed. This alternative adder cell structure performs better in terms of power dissipation, propagation delay and power-delay-product (PDP) when compared with 26T SR-CPL and other adder cells implemented using conventional logic styles. As compared with 26T SRCPL adder cell, the proposed adder cell reduces power by 23.15%, delay by 6.15% and PDP by 27.91%. This design is carried-out using a TSMC 45nm CMOS technology in Cadence Virtuoso Analog Design Environment at 45nm technology and simulated using Spectre simulator. This adder cell can be used as a computation element in various DSP architectures and microprocessors resulting in high performance.

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In this paper, a low power implicit type pulsed flip-flop (PFF) using self-driven pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. The pass transistor logic driven by generated clock pulse is used directly to drive the output of the flip-flop. The proposed design is compared with the conventional implicit type data close to output (ip-DCO) flipflop. As compared to the conventional pulse triggered flipflop, the proposed pulsed flip-flop (PFF) design features best speed, power and power-delay-product performance. The proposed technique is implemented using HSPICE CMOS 90nm technology. The average power consumption for 50% switching activity is reduced by 12.75% as compared to conventional ip-DCO.