Design of low power memory architecture using 4T content addressable memory cell

Image processing devices plays a vital role in several applications like medical, security, biometric etc. The devices ranges from portable size to larger machines with and without Human Computer Interface possibilities. As the image processing and human computer interface system application requires higher memory requirements, the power and area should be small. Searching of data is a high priority work in image classification. To perform high speed search through hardware Content Addressable Memory is used. But the circuit suffers from higher power consumption, precharging issues and low performance. For longer word length the elimination of precharge is needed. So for high speed applications self-controlled precharge-free CAM (SCPF-CAM) is suitable. A 4T hybrid self controlled pre charge free Content Addressable Memory is proposed in this paper using CMOS 32nm technology. The observation shows that the circuit works at high speed, minimizes the search time and has high performance operation. When compared to the conventional SCPF-CAM, 8T CAM the proposed design reduces the number of transistors. The reduction in area is about approximately 20% and can be used in low power and low energy applications. In Synopsis HSPICE Predictive technology models were used for the implementation in 32nm CMOS technology. The work will be extended in future using FinFET technology where the leakage current can be minimized.

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Design of low power memory architecture using 4T content addressable memory cell

Cited by 2 publications

References 22 publications

Design and Comparative Valuation of an MSML Based Low Power Content Addressable Memory Cell

Design and Comparative Valuation of an MSML Based Low Power Content Addressable Memory Cell

Low power CMOS based Self Controlled Precharge Free Content Addressable Memory with Minimum area for Image Processing Devices

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