Design of Low Power Dual Edge Triggered Flip Flop Based On Signal Feed through Scheme

Abstract

A low power dual edge triggered flip flop based on a signal feed through scheme is presented. The power consumption is the major problem in circuit design. The proposed deign reduces power and delay compared to explicit pulse triggered flip flop. Reducing the number of transistor in the stack and increasing the number of charge path leads to higher operational speed compared to others flip-flops. Double-edge-triggered flip flops (DETFFs) are recognized as power-saving flip flops. The dual edge triggered design operates in a low voltage range and hence it is suited for low voltage application. This flip flop uses weak feedback transistor but without static power consumption. This reduces leakage current and thus saves the power. By using low clock frequency high throughput can be achieved. The simulation is done using Tanner EDA Tool v14 with CMOS 90nm technology.