Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips

Abstract

Complex QR factorisation is a fundamental operation used in various applications such as adaptive beamforming and MIMO signal detection. In this paper, based on Givens rotation scheme, a high-throughput, fully parallel complex-valued QR factorisation (CQRF) design is presented. It features the lowest computing complexity in various factorising schemes and indicates no BER performance loss when applied to a MIMO signal detection system. Via carefully plotted scheduling, one CQRF computation can be completed in eight clock cycles. In hardware design, a low complexity and look-up-table-free CORDIC algorithm is employed to implement the rotation operations. Further design optimisations, such as hardware sharing of common modules and reduction of register usage by shortening the variable's life span, are also applied. Sized 22 and 44 chip designs largely following the IEEE 802.11n standard are developed. The implementation results in TSMC 0.18 um process technology show that the proposed 44 design, with a gate count of only 134.6 K, is capable of performing 15 M CQRFs per second. The measured power consumption is 196.3 mW at 120 MHz. Compound performance indexes such as area-time product and energy consumption per CQRF also indicate significant performance edges of the proposed designs

Block-Wise QR-Decomposition for the Layered and Hybrid Alamouti STBC MIMO Systems: Algorithms and Hardware Architectures

“…The architecture in [41] is for the QRD of the augmented channel matrix, which is to be used with the minimum mean squared error preprocessing to provide better detection performance for the tree traversal. The architectures in [23], [24], [26], [29] compute the R-matrix only. If these architectures compute both the -and -matrices, they require larger processing cycles and longer processing latencies.…”

“…If these architectures compute both the -and -matrices, they require larger processing cycles and longer processing latencies. To account for such unequal computations, the QRD rate [26] or throughput [24], which represents the average number of matrices that an architecture can process per second, is normalized with respect to technology and is computed by (23) where if the architecture outputs both -and -matrices and if the architecture outputs -matrix only. The results in Table VII reveal that for QRD of the same 4 4 (equivalent) channel matrices, our BCGR-TSA can perform with the highest QRD throughput rate.…”

“…Two different kinds of angle representations are used. The look-up-table free [24] representation is referred to as the angle represented by 9 bits, , where each bit indicates the direction of the micro-rotation in an iteration; the conventional angle representation is referred to as the angle represented by a 16-bit number . Take the CORDIC modules of PE #1 in Fig.…”

“…As compared with the TACR-TSA, our BCGR-TSA requires approximately 3/4 CORDIC modules for large . Also, our BCGR-TSA requires fewer processing cycles [26], which is called the pipelining period in [24] and is referred to as the number of clock cycles that a new can be input to the TSA, than that of the TACR-TSA. Remember that 3 pipeline registers are inserted in a CORDIC module.…”

A high-speed QR decomposition processor for carrier-aggregated LTE-A downlink systems

“…Moreover, HT works with columns instead of scalar elements, and thus is better for data-level parallelism. However, previous studies have suggested that the computational complexity of HT is very high, preventing it from being used in hardware implementation [3].…”