Previous cryogenic electronics studies are mostly at 77K and 4.2K. Cryogenic characterization of a 0.18µm standard bulk CMOS technology (operating voltages: 1.8V and 5V) is presented in this paper. Several NMOS and PMOS devices with different width to length ratios (W/L) were extensively tested and characterized under various bias conditions at sub-kelvin temperature. In addition to devices dc characteristics, the kink effect and current overshoot phenomenon are observed and discussed at sub-kelvin temperature. Especially, the current overshoot phenomenon in PMOS devices at sub-kelvin temperature is shown for the first time. The transfer characteristics of MOSFET devices (1.8V W/L = 10µm/10µm) at sub-kelvin temperature are modeled using the simplified EKV model. This work facilitates the CMOS circuits design and the integration of CMOS circuits with silicon-based quantum chips at extremely low temperatures.
A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/µs and -93 V/µs for 10 pF capacitive load. The static power of the circuit is only 79µW.
Optimization of analog circuits relies on engineers’ experience and intuition to find suitable parameters to satisfy circuit specifications. This job is highly labor-intensive, highly repetitive, and time-consuming, but the optimized circuit is sub-optimal. In this paper, the evolutionary strategy is proposed to optimize analog circuit design strategy. The filter designed by engineers and operational amplifier with random generated instances’ parameters are included, and the S parameters of the filter and the gain and dynamic power consumption of the operational amplifier are optimized respectively. The simulation results show that the filter and operational amplifier can be further optimized by using the evolutionary strategy. This method can greatly reduce the workload of analog circuit designers, improve the performance of analog circuits and shorten the design cycle.
A novel power-efficient analog buffer at Liquid Helium Temperature (LHT) is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit achieves a slew-rate of +36 V/µs and -33.8 V/µs for 10 pF capacitive load. The static power of the circuit is only 55.7µW.
This paper presents low power dissipation, low phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology at liquid helium temperature (LHT). First, the characterization and modelling of CMOS at LHT are presented. The temperature-dependent device parameters are revised and the model then shows good agreement with the measurement results. The ring oscillator is then designed with energy efficiency optimization by application of forward body biasing (FBB). FBB is proposed to compensate for the threshold voltage (VTH) shift to preserve the benefits of the enhancement of the carrier mobility at 4.2K. The delay per stage (τp), the static current (ISTAT), the dynamic current (IDYN), the power dissipation (P) and the phase noise (L(foff)) are analyzed at both 298 K and 4.2 K, with and without FBB. The performance of the designed RO in terms of speed (τp=179ps), static current (23.55nA/stage), power dissipation (2.13μW) and phase noise (-177.57dBc/Hz@1MHz) can be achieved at 4.2K with the supply voltage (VDD) reduced to 0.9V.
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