A cryogenic low power CMOS analog buffer at 4.2K

Abstract

A novel power-efficient analog buffer at Liquid Helium Temperature (LHT) is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit achieves a slew-rate of +36 V/µs and -33.8 V/µs for 10 pF capacitive load. The static power of the circuit is only 55.7µW.