A new approach to obtain the wavelet transform with easily constructed analogue circuits is presented. It is shown that the impulse response of a bandpass biquad filter satisfies the conditions to be considered a mother wavelet. Using this, an integrated circuit performing the wavelet transform at 16 scales along eight octaves has been designed. The design has CMOS transistors working in the subthreshold region with a total power consumption of 650 nW. On-chip measurements are reported.Introduction: Traditionally, the wavelet transform (WT) is implemented numerically or algorithmically. Recently, there have been significant advances in the analogue implementations of this transform and its practical applications [1,2]. The analogue realisation is attractive for low power signal processing in areas such as portable and bio-implantable devices. Currently, the common analogue approach is to obtain each scale of the WT by means of convolution in a bandpass continuous filter, the impulse response of which has the wavelet shape. References [1,2] have applied this principle with favourable results. These works show efforts to obtain good approximations of the known classical wavelets: the Morlet wavelet [1], and the first derivative of a Gaussian [2]. However, to obtain a good approximation, the filters have to be of high order, since the shape of classical wavelets is not the natural impulse response of the simpler analogue filters. In this Letter, we show that the impulse response of a bandpass biquad filter is a mother wavelet.

A new configuration of the flipped voltage follower (FVF) offering class-AB operation is presented. The idea uses a bulk-driven transistor instead of the constant current source of the typical FVF topology. This feature enhances the sourcing capability for class-AB operation and the symmetrical slew rate. The key element is changing the basic structure of the original FVF circuit with no additional devices. A detailed analysis of the circuit and simulations using Spice are presented. The experimental results from a manufactured circuit prototype using CMOS 0.35 μm technology demonstrate the feasibility of the proposal.

We propose two approximations of the inverse wavelet transform implemented with a voltage adder and two analog filters. They work together with a set of scaled band-pass analog filters that perform the wavelet transform of a continuous time signal. With this approach an integrated circuit has been fabricated. On-chip measurements demonstrate signal to reconstruction error ratios up to 25.8 dB.

The multiple-input floating-gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple-input floating-gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple-input floating-gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Figure 2. (a) Intrinsic interface for n-input gates MIFGMOS and (b) MOS interface with a new terminal added (c) capacitances are represented only. 678 A. S. MEDINA-VAZQUEZ ET AL.Figure 3. ψ s vs. (V 1 À V FB ).Simulation results for the intrinsic interface. Voltage V 1 is applied to the control gate CG 1 and swept while V 2 voltage (applied to the control gate CG 2 ) is used as a parameter. V FB = 0.6 V, t ox = 8e À 9 m, W = 0.3 μm, W = 0.1 μm, C 1 = 50 fF, C 2 = 20 fF.

Abstract:A technique for the implementation of a programmable grounded and floating resistors is presented. The grounded version of the resistor has been implemented in a standard CMOS technology, where a set of digital inputs allows the programming of the circuit. The performance of the circuit is shown by means of DC, AC, Transient and Monte Carlo simulations. Measurements on a 0.35 µm CMOS physical implementation are presented. Additionally, an application of the proposed circuit in programmable filters is described.

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This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.