Analysis of the floating‐gate transistor using the charge sheet model

Abstract

The multiple-input floating-gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple-input floating-gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple-input floating-gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Figure 2. (a) Intrinsic interface for n-input gates MIFGMOS and (b) MOS interface with a new terminal added (c) capacitances are represented only. 678 A. S. MEDINA-VAZQUEZ ET AL.Figure 3. ψ s vs. (V 1 À V FB ).Simulation results for the intrinsic interface. Voltage V 1 is applied to the control gate CG 1 and swept while V 2 voltage (applied to the control gate CG 2 ) is used as a parameter. V FB = 0.6 V, t ox = 8e À 9 m, W = 0.3 μm, W = 0.1 μm, C 1 = 50 fF, C 2 = 20 fF.

On the methodology of calculating volume charge density in a MIFGMOS substrate using Poisson’s equation

“…Recently, an electric field analysis was performed to estimate the charge density stored in the trapping layer of a Silicon (Polycrystalline silicon) -Oxide (Silicon dioxide) -Ntride (Silicon Nitride) -Oxide -(Silicon dioxide) -Silicon (Polycrystalline silicon) memory flash (Li et al, 2011). A mathematical model was proposed based on the parallel connection of the capacitors.…”

Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits

“…Quasi-floating gate requires a high value resistor, R Large , typically implemented by a single transistor connected to a DC biasing voltage and a capacitor, C i , connected to the AC input voltage in order to work properly. Low voltage analog circuits have been widely improved by using these Bulk Driven [4,5,6,7,8,9,10,11,12,13,14,15,16] and Floating Gate [17,18,19,20,21,22,23,24,25,26,27,28,29,30] techniques, and from them we derive the new technique presented in following section.…”