This letter details a novel floating-bulk transistor technique for low-voltage design. The approach is derived from two previous wellknown techniques: bulk-driven and quasi floating-gate. The floating-bulk technique uses an input capacitive coupling through a floating bulk of a PMOS allowing modulation of the drain current. A fabricated commonsource amplifier was tested on CMOS 0.5 µm technology and the feasibility of the proposal was demonstrated.
We introduce ex p erimental, modeling and simulation results of the electrical p erformance of 28nm FETs, operated under the action of an external magnetic field B. Negative resistance and magneto-current am p lification are some of the effects discussed through this research com p ilation done within the Microelectronics research
In this work we present the design and fabrication of a test chip to be used for the characterization of the main electrical, mechanical and thermal properties of the structural materials involved in the development of polysilicon-based electrothermal actuators. With this combined bulk/surface micromachined chip, parameters such as Young's modulus (E), stretching or compression stresses (±σ), stress gradients (± Δε), electrical resistivity (ρe), doping level (n+), thermal conductivity (κ), and thermal capacitance (C) can be obtained. This test chip was fabricated using the PolyMEMS-INAOE fabrication process, in which the main materials involved are silicon oxide, silicon nitride, phosphosilicate glass, aluminum, mono-and polycrystalline silicon. In this combined micromachining technology, the polysilicon film is the main structural material and it is used to build the mechanical actuators.
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