We introduce an experimental alternative way of looking into the charging and discharging mechanism inside a high-k stacked oxide of a metal-gate strained n-type Field-Effect-Transistor (nFET). This alternative way reproduces a memory and negative resistance effect by biasing the nFET device in a non-conventional way. This is achieved by forward-biasing the drain-bulk junction and by setting the gate electrode in a high-impedance mode. The produced negative resistance effect (NRE) has a controllable peak-to-valley current ratio (PVCR) that goes from about 3.0 up to a value of 5.5 at room temperature. The PVCR increases up to 8.35 at T=225 K and reduces to 2.84 at T=375 K in a linear trend. The memory effect is observed when the drain-bulk junction voltage is swept from low to high values and back from high to low values. From low to high forward drain-bulk bias the NRE shows up and vanishes when coming back from high to low forward drain-bulk bias. The NRE and memory effects are attributed to a coupled-gate oxide charging/discharging mechanism with an induced bipolar transistor action in the channel of the FET.
A numerical simulation methodology for incorporating thermo-magnetic effects on the MOSFET gate tunneling current is introduced. The methodology is based on the solution of the Schrödinger-Poisson coupled system, which allows simulating the influence of a static magnetic field and temperature on the wavefunctions and gate tunneling current of MOSFET devices. In addition to the preliminary results on the simulation methodology, experimental results on the effect of the magnetic field on the subthreshold slope, the off-current, and transconductance, are also introduced. The proposed simulation methodology, in conjunction with experimental data, is useful for device degradation and reliability studies in nano-scaled MOSFET devices. This experimental characterization technique sets also the basis for the development of a magnetic force nanoscopy technique, where the conductive properties, thanks to the Lorentz force, can be two-dimensionally mapped over the nano-scaled MOSFET channel plane.INDEX TERMS Nano-scaled MOSFETs, asymmetric tunneling current, magnetic field, temperature.L. ARTURO SARMIENTO-REYES received the Ph.D. degree in electronic engineering from the
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