2020
DOI: 10.1587/elex.17.20190748
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Floating-bulk transistors: An alternative design technique for CMOS low-voltage analog circuits

Abstract: This letter details a novel floating-bulk transistor technique for low-voltage design. The approach is derived from two previous wellknown techniques: bulk-driven and quasi floating-gate. The floating-bulk technique uses an input capacitive coupling through a floating bulk of a PMOS allowing modulation of the drain current. A fabricated commonsource amplifier was tested on CMOS 0.5 µm technology and the feasibility of the proposal was demonstrated.

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Cited by 2 publications
(5 citation statements)
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“…2a [12] and is based on Flipped-Voltage Followers (FVF) [13], which are marked in square rectangles. Floating-bulk transistor [30].…”
Section: Conventional Four-quadrant Multipliersmentioning
confidence: 99%
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“…2a [12] and is based on Flipped-Voltage Followers (FVF) [13], which are marked in square rectangles. Floating-bulk transistor [30].…”
Section: Conventional Four-quadrant Multipliersmentioning
confidence: 99%
“…The latter eliminates the need for this 𝑉 𝑇𝐻 , yielding to lower supply requirements; however, the signal swing at the bulk terminal must be small to prevent large currents by forward biasing the substrate-source junction of the transistor; it also has found many applications [23]- [29]. A recently reported technique that avoids the aforementioned drawbacks is the Floating-Bulk (FB) technique [30], shown in Fig. 2b.…”
Section: Proposed Four-quadrant Multipliermentioning
confidence: 99%
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“…However, in the real case, the charge accumulated in the N‐well can flow through the substrate junction, which is reverse biased. By equating the two currents, voltage V DB has to be small (some tens of millivolts) due to exponential dependence on the base current 15 . Such result guarantees that floating body of transistor do not cause any additional current loss during cut‐off.…”
Section: The Proposed Designmentioning
confidence: 99%