The automatic control of the matching impedance in chip-to-chip interconnections is described. The proposed method is based on an optimization algorithm that uses the sign of error and the sign of the coupling branch current. A possible implementation of the system is described and computer simulations at the behavioral level are presented.
Abstract:A technique for the implementation of a programmable grounded and floating resistors is presented. The grounded version of the resistor has been implemented in a standard CMOS technology, where a set of digital inputs allows the programming of the circuit. The performance of the circuit is shown by means of DC, AC, Transient and Monte Carlo simulations. Measurements on a 0.35 µm CMOS physical implementation are presented. Additionally, an application of the proposed circuit in programmable filters is described.
The multiple-input floating-gate transistor is a semiconductor device that has found wide application in digital and analog electronic integrated circuits. Simulating an electronic circuit is an essential step in the design flow, prior to manufacturing. Therefore, an advanced model for the multiple-input floating-gate transistor is needed for analog design. This paper shows a method for adapting the charge sheet model for advanced models of the device. In addition, the problem of obtaining the drain to source current numerically as a function of external voltages is addressed. Furthermore, important plots are presented in order to clarify the behavior of the concerned device. The small signal analysis of the device is included. This summary may be interesting to those seeking to model the multiple-input floating-gate transistor, looking for alternatives to analog electronic design, needing low operating voltage, generating new design strategies, or wishing to understand of the operation of the device or the use of alternatives to implement analog circuits. Figure 2. (a) Intrinsic interface for n-input gates MIFGMOS and (b) MOS interface with a new terminal added (c) capacitances are represented only. 678 A. S. MEDINA-VAZQUEZ ET AL.Figure 3. ψ s vs. (V 1 À V FB ).Simulation results for the intrinsic interface. Voltage V 1 is applied to the control gate CG 1 and swept while V 2 voltage (applied to the control gate CG 2 ) is used as a parameter. V FB = 0.6 V, t ox = 8e À 9 m, W = 0.3 μm, W = 0.1 μm, C 1 = 50 fF, C 2 = 20 fF.
A system for self tuning of on-die terminators in current mode off-chip signaling is presented. The proposed method is based on an algorithm that uses the sign of the impedance matching error and the sign of the coupling branch current to perform the self tuning operation. The circuit implementation of the system is described and computer simulations at the transistor level are presented for process, temperature and load impedance variations.
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