MOSFET characterization and modeling at cryogenic temperatures

IEICE Electron. Express

et al. 2021

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A novel power-efficient analog buffer at Liquid Helium Temperature (LHT) is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit achieves a slew-rate of +36 V/µs and -33.8 V/µs for 10 pF capacitive load. The static power of the circuit is only 55.7µW.

Section: Cryogenic Modelmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A cryogenic low power CMOS analog buffer at 4.2K

Huang

IEICE Electron. Express

et al. 2021

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“…For short-channel mode of operation, the ℎ is defined as ℎ = (5) where is defined as the value of electric field resulting in half the carrier velocity expected from low field mobility, is the gate-length and is 2/3 for long-channel devices in saturation region and 2~3 times greater for the case of shortchannel devices. Note the absence of any dependency on the number of stages in (3).…”

Section: Circuit Descriptionmentioning

confidence: 99%

0.18μm CMOS Ring Oscillator at Liquid Helium Temperature

2019 IEEE 3rd International Conference on Circuits, Systems and Devices (ICCSD)

et al. 2019

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This paper presents low power dissipation, low phase noise ring oscillators (ROs) based on Semiconductor Manufacturing International Corporation (SMIC) 0.18μm CMOS technology at liquid helium temperature (LHT). First, the characterization and modelling of CMOS at LHT are presented. The temperature-dependent device parameters are revised and the model then shows good agreement with the measurement results. The ring oscillator is then designed with energy efficiency optimization by application of forward body biasing (FBB). FBB is proposed to compensate for the threshold voltage (VTH) shift to preserve the benefits of the enhancement of the carrier mobility at 4.2K. The delay per stage (τp), the static current (ISTAT), the dynamic current (IDYN), the power dissipation (P) and the phase noise (L(foff)) are analyzed at both 298 K and 4.2 K, with and without FBB. The performance of the designed RO in terms of speed (τp=179ps), static current (23.55nA/stage), power dissipation (2.13μW) and phase noise (-177.57dBc/Hz@1MHz) can be achieved at 4.2K with the supply voltage (VDD) reduced to 0.9V.

“…Temperature‐dependent parameters are revised at 4.2 K and the model shows good agreement with measurement results after kink correction. This work is the first BSIM3V3 SPICE model range down to 4.2 K for

0.18 μ m

CMOS technology [5]; the model can be applied directly to devices and circuits electronic design automation simulations.…”

Section: Introductionmentioning

confidence: 99%

“…By this token, the transconductance of differential pair is determined by the transconductance of the input transistor. At cryogenic temperature, the MOSFETs' Gm increases obviously which means that for the same power budget the circuits have a wider bandwidth at liquid helium temperature [2]. As for buffer circuit, operating at cryogenic temperature could get analogous performance but consume less power.…”

mentioning

confidence: 99%

Modelling and kink correction of bulk CMOS at liquid helium temperature

et al. 2019

Electron. lett.

Self Cite

A novel power-efficient analog buffer at liquid helium temperature is proposed. The proposed circuit is based on an input stage consisting of two complementary differential pairs to achieve rail-to-rail level tracking. Results of simulation based on SMIC 0.18µm CMOS technology show the high driving capability and low quiescent power consumption at cryogenic temperature. Operating at single 1.4 V supply, the circuit could achieve a slew-rate of +51 V/µs and -93 V/µs for 10 pF capacitive load. The static power of the circuit is only 79µW.